startup_ARMCA15.S in CCS 6.1.3 can cause an Undefined Instruction Exception when enabling the VFP

Chester Gillon said:

On starting debug sessions, sometimes the program failed to reach main. E.g. the following sequence is repeatable:

1) Execute a reboot command in EVMK2H BMC to perform a full reset (without having to power-cycle).

2) Start a debug session, and the program doesn't reach main. When suspend the program a Undefined Instruction Exception has occurred on the Cortex-A15.

3) Terminate the failed debug session, and start a new debug session. This time the program reaches main.

1) After a full reset, the CPACR register was zero when the entry point was reached, meaning access to the CP10 and CP11 co-processor registers was disabled.

2) While the code in startup_ARMCA15.S did write to the CPACR register to enable access to the CP10 and CP11 co-processor registers, the lack of the ISB synchronization instruction meant that when the FMXR  FPEXC,r0 instruction attempted to write to the FPEXC an Undefined Instruction Exception occurred.

The ARMv7-A Architecture Reference Manual notes that FMXR  FPEXC,r0 instruction will generate an Undefined Instruction Exception if access to the CP10 and CP11 co-processor registers is disabled.

3) After terminating the failed debug session, when started a new debug session (without performing a full reset) the CPACR register was 0x00F00000 when the entry point was reached, meaning access to the CP10 and CP11 co-processor registers was enabled (as a result of the previous run). Therefore, on this run FMXR  FPEXC,r0 instruction no longer generates an Undefined Instruction Exception.

Chester Gillon said:

Also, it looks like the startup_ARMCA8.S and startup_ARMCA9.S have the same problem, although I haven't tested them to see if an Undefined Instruction Exception can occur.

.if __ARM_PCS_VFP == 1
@
@ Enable NEON extensions and the VFP. Must be done before entering user mode.
@
        MRC   p15, #0, r3, c1, c0, #2    @ Read CPACR
		ORR   r3, r3, #0x00F00000        @ Enable access to CP10 and CP11
		MCR   p15, #0, r3, c1, c0, #2    @ Write CPACR
		MOV   r3, #0
      	MOV   r0,#0x40000000
        FMXR  FPEXC,r0                   @ Set FPEXC bit 30 to enable VFP
		MCR   p15, #0, r3, c7, c5, #4    @ flush prefetch buffer because of FMXR above
.endif

Using a Cortex-A9 in an OMAP4430 when the CPACR register was zero at the entry point after a power on reset, the code was able to enable the VFP without generating an Undefined Instruction Exception. i.e. unlike the Cortex-A15 can't repeat the exception. It is probably processor implementation defined behavior about if omitting an ISB synchronization instruction will cause a run time failure or not, due to the internal timing of how instructions are prefetched. The Cortex-A9 NEON Media Processing Engine Technical Reference Manual also shows an ISB instruction after writing to the CPACR register, which is sufficient justification to modify startup_ARMCA9.S to add an ISB after the write to the CPACR register.

Chester,

Thanks for reporting this; at a certain point I recall having a delay to grant the registers were properly updated before the next instruction, but somehow this disappeared from the last implementation.

>>Using a Cortex-A9 in an OMAP4430 when the CPACR register was zero at the entry point after a power on reset, the code was able to enable the VFP without generating an Undefined Instruction Exception. i.e. unlike the Cortex-A15 can't repeat the exception. It is probably processor implementation defined behavior about if omitting an ISB synchronization instruction will cause a run time failure or not, due to the internal timing of how instructions are prefetched.

I agree with you; I have been testing this code with the Sitara devices (AM3359 for CA8, AM4379 for CA9 and AM5728 for CA15) and did not experience any trouble with the current implementation.

I will update the files and perform tests on some Keystone II boards I have here.

Thank you again for reporting this and I apologize for the trouble,
Rafael

desouza said:

I will update the files and perform tests on some Keystone II boards I have here.

Just noticed that the ccsv7\ccs_base\arm\include\startup_ARMCA15.S installed by CCS 7.2.0.00013 and TI Emulators 7.0.48.0 still omits the ISB instruction before enabling VFP.