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CCS/AM5728: Specify the core sequence for debug configuration

Kia
Prodigy 150 points
Part Number: AM5728

Tool/software: Code Composer Studio

Hi,

I am using TI JTAG to connect to Sitara EVM. To load the code into any core, first, I have to connect the JTAG without loading the code. Then connect the ARM A15 core. This will execute the gel file for A15 and generates all the clocks for all other cores, then I can load my code for any other cores manually. I want to know if I can automate this process. Here is my question:

How can I specify the sequence of connecting/loading for JTAG using 'Debug COnfiguration'? I want the A15 core connected first and after the A15 Gel file execution, other cores get connected automatically.

Thanks

  • 0
    TI__Guru**** 464351 points

    Hello,

    You can always create a DSS initialization javascript to automate those actions. This initialization script can be specified in the debug configuration

    Thanks

    ki

  • 0 in reply to Ki
    Prodigy 150 points
    Hi Ki,
    But my question was about if I can ask CCS to connect to one specific core before all other cores(using one signle debug configuration). For Siatra when I have code for multiple cores, CCS always first connect to ARM9, which generates error. The master core for Sitara is A15. Is there any other option without external scripts.
    Thanks
  • 0 in reply to Kia
    TI__Guru**** 464351 points
    How are you launching the debug session? Do you have a project for one of the slave processors (ARM9, M4, etc) and wish to simply press the "Debug" button to have CCS launch a project debug session, first connect to the A15 and then connect to the slave processor and load the program?
  • 0 in reply to Ki
    Prodigy 150 points

    The answer to your question is: Yes.

    Currently, I have one debug configuration, that first connect only to A15. This will initialize all the memories first. Then I have another debug configuration for A15+C66. In this Debug configuration by default:

    1- The C66 code is loaded and then the C66 executes the code until 'main'.

    2- The A15 is connected last and this init the memory and reset all other cores and then load A15 codes into memory.

    2-1: Because the gel script for A15 reset all other cores,  the Program Counter of C66 is now pointing to 0x80000(and not to the 'main').

    3- At this point, I have to 'reload' the code to reinitialize the PC for C66( I have the same problem for all other cores).

    This 3 steps loading for 'A15+any other core' is caused by the A15 being the last core in the JTAG configuration file. 

    Thanks

    Kia

  • 0 in reply to Kia
    Prodigy 150 points

    Hi Ke,

    Can you please answer my question?

    Thanks

    Kia

  • 0 in reply to Kia
    TI__Guru**** 464351 points
    HI Kia,
    Sorry for the delay. The best way is via a init JS script so you can explicitly control the order. You could also create a full DSS javascript and run it from the scripting console. That is a more common option I see for people who wish to do what you are looking for.

    In the past, people used be able to specify certain CPUs as master and slave to control the connection order. While this designation still exists, it doesn't seem to have the same effect as in the past. I will follow up with engineering team here to confirm.

    Thanks
    ki