Hi,
I'm facing a unusual problem. I'm working with EVM6678LE
I have one project to each core, a custom platform, and a conditional linker file in order to each core to know only his own memory space (on-chip and a section of DDR3).
I've started the projects from scratch but when I added more libraries (like NDK e PDK), got this problem at linktime:
C:\ti\ccsv5\utils\bin\gmake -k all
'Building target: ProjetoMaster.out'
'Invoking: C6000 Linker'
"C:/ti/ccsv5/tools/compiler/c6000_7.3.4/bin/cl6x" -mv6600 -g --display_error_number --diag_warning=225 --abi=eabi -z -m"ProjetoMaster.map" --define=CORE0=1 --verbose_diagnostics --warn_sections --display_error_number -i"C:/ti/ccsv5/tools/compiler/c6000_7.3.4/lib" -i"C:/ti/pdk_C6678_1_0_0_19/packages/ti/platform/evmc6678l/platform_lib/lib/debug" -i"C:/ti/ccsv5/tools/compiler/c6000_7.3.4/include" --reread_libs --rom_model -o "ProjetoMaster.out" -l"./configPkg/linker.cmd" "./sistema/resourcemgr.obj" "./sistema/rede.obj" "./sistema/platform_osal.obj" "./servidor_web.obj" "./Pumatronixmulticore.obj" -l"ti.platform.evm6678l.ae66" -l"libc.a" "C:/Users/Weber/workspace_v5_2_teste/superlinker.cmd"
<Linking>
warning #10247-D: creating output section "platform_lib" without a SECTIONS
specification
undefined first referenced
symbol in file
--------- ----------------
CfgAddEntry ./sistema/rede.obj
CfgEntryDeRef ./sistema/rede.obj
CfgEntryGetData ./sistema/rede.obj
CfgGetEntry ./sistema/rede.obj
CfgGetImmediate ./sistema/rede.obj
CfgRemoveEntry ./sistema/rede.obj
NtIPN2Str ./sistema/rede.obj
System_printf ./sistema/rede.obj
TaskCreate ./sistema/rede.obj
TaskExit ./sistema/rede.obj
TaskSleep ./sistema/rede.obj
_oscfg ./sistema/rede.obj
inet_addr ./sistema/rede.obj
mmZeroInit ./sistema/rede.obj
error #10234-D: unresolved symbols remain
error #10010: errors encountered during linking; "ProjetoMaster.out" not built
The weird is: My projects are RTSC, and the libraries are checked correctly, also the environment variables looks ok.
If I go to project options > Linker > Linker Output and check the box 'Produce a relocatable output module' the project compile and links ok. However, while trying to debug via jtag, this error appears:
C66xx_0: Loader: One or more sections of your program falls into a memory region that is not writable. These regions will not actually be written to the target. Check your linker configuration and/or memory map.
C66xx_0: Trouble Writing Register PC: (Error -1176 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.681.0)
I am sure that the gel file is ok, this error started when the project grew bigger and started using more libraries.
My linker file content for core 0 is:
.text > CORE0_L2_SRAM
xdc.meta > CORE0_L2_SRAM
.vecs > CORE0_L2_SRAM
.stack > CORE0_L2_SRAM
.bss > CORE0_L2_SRAM
.cio > CORE0_L2_SRAM
.const > CORE0_L2_SRAM
.data > CORE0_L2_SRAM
.switch > CORE0_L2_SRAM
.sysmem > CORE0_L2_SRAM
.far > CORE0_L2_SRAM
.args > CORE0_L2_SRAM
.ppinfo > CORE0_L2_SRAM
.ppdata > CORE0_L2_SRAM
/* COFF sections */
.pinit > CORE0_L2_SRAM
.cinit > CORE0_L2_SRAM
/* EABI sections */
.binit > CORE0_L2_SRAM
.init_array > CORE0_L2_SRAM
.neardata > CORE0_L2_SRAM
.fardata > CORE0_L2_SRAM
.rodata > CORE0_L2_SRAM
.c6xabi.exidx > CORE0_L2_SRAM
.c6xabi.extab > CORE0_L2_SRAM
So I put everyting on Core 0 internal's memory.
I really dont know what can possibly causing this weird error. Anyone can help?
Weber