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Cortex-R4 Linker doesn't generate BLX for Mode Change function calls

Pashan None
Genius 5660 points
Other Parts Discussed in Thread: TMS570LS3137

Hello Support,

I am using 4.9.7 version of ARM Compiler with TMS570LS3137 device [Cortex-R4 core]

According to the page shown below, for Cortex-R4 ARM Compiler, whenever there is a function call from THUMB Mode to ARM Mode happens, Linker replaces the function call with BLX Instruction.

But in the attached ZIP file, if you see within Out folder's ECC99.map file, there is instead Veneer Section is generated.

Please let me know if it is a BUG in the Linker 4.9.7.

I have attached the Page from the following link with Markup for easy understanding.

ftp://ftp.ti.com/pub/private-cs/armcgt_releases/getting_started/TMS470CompilerGettingStartedGuide.htm

In the ZIP file, once you unzip using FOLDER Option, you can run the compile_TI.bat file in order to rebuild the whole software provided you change the COMPILER Installation path within the BAT file according to your PC setup.

Let me know if you need any more information in order to debug this issue.

Thank you.
Regards
Pashan

 

Linker_Bug_BLX_Short.zip
  • 0
    Genius 5660 points

    Hello Support,

    The above mentioned BLX Instruction instead of Veneer was implemented in Linker 4.1.2 version as mentioned in the following Link:

    ftp://ftp.ti.com/pub/private-cs/armcgt_releases/docs/CGTNew4_1_2.html

    Thank you.
    Regards
    Pashan

     

  • 0 in reply to Pashan None
    TI__Guru**** 251180 points

    You are building for EABI (with build setting --abi=eabi), so none of this documentation about ti_arm9_abi or tiabi applies.

    I'm not sure what is going on.  I think you are getting a combination trampoline and veneer.  It might have something to do with the fact that the destination of the call is hand-coded assembly.  The person who knows these details the best is out today, so I cannot answer this with any certainty.  I plan to get back to you.

    Thanks and regards,

    -George

  • 0 in reply to George Mock
    TI__Expert 4540 points

    The issue here is that the compiler did tail call optimization on the Setup_Memory_Protection function. The function only calls MPU_Initialize_ARM, so the compiler replaced the branch and link (BL) instruction with a normal branch (B). The benefit is that the function no longer has to save and restore the link register and when MPU_Initialize_ARM returns it will return to the caller of Setup_Memory_Protection. The problem arises because Setup_Memory_Protection is a thumb function and MPU_Initialize_ARM is an arm function. The linker cannot convert the normal branch instruction to a branch and exchange (to switch to arm mode) because there is no form of BX that takes a literal address. The linker is then forced to generate a veneer to perform the state change. The compiler cannot know when it performs the tail call optimization what state the callee will be in. I suggest that you compile the Setup_Memory_Protection function in ARM mode to avoid the veneer. You can use the CODE_STATE pragma to avoid having to change your build options.