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Undefining VFP_FP option in CCS

HS Park
Prodigy 180 points

Other Parts Discussed in Thread: AM5728

Hi Rahul,

Thank you for your reply.

Another issue occurred on ARM CorePac while booting.
The instruction "vmsr fpexc, r0" doesn't work.
According to e2e.ti.com/.../345672 , it seems to be because of non-secure boot mode.
If so, I'd like to skip vmsr instruction as a workaround.

As I know, the instruction "vmsr fpexc, r0" is only activated in case __VFP_FP__ is defined.
Is there any CCS options to undefine __VFP_FP__?
Or any other workaround to make "vmsr fpexc, r0" work?

  • TI__Guru**** 171839 points

    Hi,

    The __VFP_FP__ is a GCC macro usually defined when one or more floating point options are enabled.

    For an AM5728 that uses a Cortex A15, for example, usually floating point support is enabled by setting both the options -mfloat-abi=hard and -mfpu=vfpv4 

    I suggest you take a look at how the options of your project.

    Unfortunately I am not very familiar with the 66AK2H family of devices to comment about specific methods to enable the VFP, but one thing you may want to be sure is to check if any GEL initialization is somehow preventing this initialization from happening. The way I usually test this is to create a small baremetal project that allocates everything to MSMC RAM (you don't need to pre-initialize the internal MSMC) and remove any initialization scripts (GELs) from your target configuration file (.ccxml).

    For details on how to add/remove GEL files from your target configuration file please check:
    processors.wiki.ti.com/.../GSG:Adding_GEL_files_to_a_target_configuration_v5

    Hope this helps,
    Rafael

  • Guru 92251 points

    HS Park said:
    The instruction "vmsr fpexc, r0" doesn't work.

    Do you mean "Undefined Instruction Exception" occurs, or something else?

    Also are you using a bare metal program or something else?

    The reason for asking is that previously found the startup_ARMCA15.S file supplied with CCS for use in bare metal programs could cause an Undefined Instruction Exception when enabling the VFP on a CortexA15 - see https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/531151 for details and a suggested code change.

  • in reply to desouza
    Prodigy 180 points
    Hi,

    Sorry for my late reply.

    Actually this thread was separated from e2e.ti.com/.../565317.

    I'm evaluating EVMK2H.
    And I'd like to boot DSPs and ARMs using RBL in DSP master boot mode.

    I made one big image that contains all DSPs and ARMs images.
    I checked DSP Core 0 generates IPC interrupts to other cores to wake up them.

    The problom is that ARM Core 0 doesn't boot correctly since the instruction "vmsr fpexc, r0" causes the undefined exception.
    I think it's because RBL makes non-secure mode and NSACR remains "Coprocessor Non-secure access disabled".
    Consequently, CP10 and CP11 are not accessible, therefore "vmsr fpexc, r0" causes the undefined exception.

    So, I'd like to know if I can skip "vmsr fpexc, r0" as a workaround.
    Or is there any way to make "vmsr fpexc, r0" work?

    Any help would be appreciated.

    Best regards,

    HS Park.
  • in reply to HS Park
    Guru 92251 points

    HS Park said:
    The problom is that ARM Core 0 doesn't boot correctly since the instruction "vmsr fpexc, r0" causes the undefined exception.

    Can you show the code prior to the  "vmsr fpexc, r0" instruction?

  • in reply to Chester Gillon
    Prodigy 180 points
    Here is my _c_int00 automatically generated by SYS/BIOS.


    c00050c8: E10F0000 mrs r0, apsr
    c00050cc: E380C0C0 orr r12, r0, #0xc0
    c00050d0: E129F00C msr cpsr_fc, r12
    c00050d4: F102001F cps #0x1f
    c00050d8: EE110F10 mrc p15, #0, r0, c1, c0, #0
    c00050dc: E3011004 movw r1, #0x1004
    c00050e0: E1C00001 bic r0, r0, r1
    c00050e4: EE010F10 mcr p15, #0, r0, c1, c0, #0
    c00050e8: F57FF06F isb sy
    c00050ec: EE300F30 mrc p15, #1, r0, c0, c0, #1
    c00050f0: E2103407 ands r3, r0, #0x7000000
    c00050f4: E1A03BA3 lsr r3, r3, #0x17
    c00050f8: 0A00001A beq #0xc0005168
    c00050fc: E3A0A000 mov r10, #0
    c0005100: E08A20AA add r2, r10, r10, lsr #1
    c0005104: E1A01230 lsr r1, r0, r2
    c0005108: E2011007 and r1, r1, #7
    c000510c: E3510002 cmp r1, #2
    c0005110: BA000011 blt #0xc000515c
    c0005114: EE40AF10 mcr p15, #2, r10, c0, c0, #0
    c0005118: F57FF06F isb sy
    c000511c: EE301F10 mrc p15, #1, r1, c0, c0, #0
    c0005120: E2012007 and r2, r1, #7
    c0005124: E2822004 add r2, r2, #4
    c0005128: E30043FF movw r4, #0x3ff
    c000512c: E01441A1 ands r4, r4, r1, lsr #3
    c0005130: E16F5F14 clz r5, r4
    c0005134: E3077FFF movw r7, #0x7fff
    c0005138: E01776A1 ands r7, r7, r1, lsr #13
    c000513c: E1A09004 mov r9, r4
    c0005140: E18AB519 orr r11, r10, r9, lsl r5
    c0005144: E18BB217 orr r11, r11, r7, lsl r2
    c0005148: EE07BF56 mcr p15, #0, r11, c7, c6, #2
    c000514c: E2599001 subs r9, r9, #1
    c0005150: AAFFFFFA bge #0xc0005140
    c0005154: E2577001 subs r7, r7, #1
    c0005158: AAFFFFF7 bge #0xc000513c
    c000515c: E28AA002 add r10, r10, #2
    c0005160: E153000A cmp r3, r10
    c0005164: CAFFFFE5 bgt #0xc0005100
    c0005168: E3A0A000 mov r10, #0
    c000516c: EE40AF10 mcr p15, #2, r10, c0, c0, #0
    c0005170: F57FF06F isb sy
    c0005174: EE110F10 mrc p15, #0, r0, c1, c0, #0
    c0005178: E3A01001 mov r1, #1
    c000517c: E1C00001 bic r0, r0, r1
    c0005180: EE010F10 mcr p15, #0, r0, c1, c0, #0
    c0005184: F57FF04F dsb sy
    c0005188: F57FF06F isb sy
    c000518c: EE080F17 mcr p15, #0, r0, c8, c7, #0
    c0005190: EE080F16 mcr p15, #0, r0, c8, c6, #0
    c0005194: EE080F15 mcr p15, #0, r0, c8, c5, #0
    c0005198: F57FF04F dsb sy
    c000519c: F57FF06F isb sy
    c00051a0: E3000000 movw r0, #0
    c00051a4: E34000F0 movt r0, #0xf0
    c00051a8: EE010F50 mcr p15, #0, r0, c1, c0, #2
    c00051ac: F57FF06F isb sy
    c00051b0: E3000000 movw r0, #0
    c00051b4: E3440000 movt r0, #0x4000
    c00051b8: EEE80A10 vmsr fpexc, r0