CCS/TMS320F28027: program will not fit into available memory location

hi,

actually we have to make single contiguous memory to avoid this error .can any one help me in making single contiguous memory.my ram file is below:

/*
//###########################################################################
//
// FILE: 28027_RAM_lnk.cmd
//
// TITLE: Linker Command File For 28027 examples that run out of RAM
//
// This ONLY includes all SARAM blocks on the 28027 device.
// This does not include flash or OTP.
//
// Keep in mind that L0 is protected by the code
// security module.
//
// What this means is in most cases you will want to move to
// another memory map file which has more memory defined.
//
//###########################################################################
// $TI Release: F2802x Support Library v230 $
// $Release Date: Fri May 8 07:43:05 CDT 2015 $
// $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\f2802xX_headers\cmd
//
// For BIOS applications add: F2802xX_Headers_BIOS.cmd
// For nonBIOS applications add: F2802xX_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2802xX_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2802xX_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\f2802xX_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2802xX
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections

Notes:
Memory blocks on F28027 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.

The L0 memory blocks is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.

Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :
/* For this example, L0 is split between PAGE 0 and PAGE 1 */
/* BEGIN is used for the "boot to SARAM" bootloader mode */

BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000050, length = 0x0003B0
PRAML0 : origin = 0x008000, length = 0x000900
RESET : origin = 0x3FFFC0, length = 0x000002

IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Tables in Boot ROM */

BOOTROM : origin = 0x3FF27C, length = 0x000D44

PAGE 1 :

/* For this example, L0 is split between PAGE 0 and PAGE 1 */
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
DRAML0 : origin = 0x008900, length = 0x000700
}

SECTIONS
{
/* Setup for "boot to SARAM" mode:
The codestart section (found in DSP28_CodeStartBranch.asm)
re-directs execution to the start of user code. */
codestart : > BEGIN, PAGE = 0
ramfuncs : > RAMM0 PAGE = 0
.text : > PRAML0, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.pinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.stack : > RAMM1, PAGE = 1
.ebss : > DRAML0, PAGE = 1
.econst : > DRAML0, PAGE = 1
.esysmem : > RAMM1, PAGE = 1

IQmath : > PRAML0, PAGE = 0
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD

/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{

IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{

IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

}
*/

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

To do any level of customization to the linker command file, a basic understanding of its purpose and syntax is required. If you are new to the TI compiler tool, the Linker chapter in the C2000 Assembly Language Tools Users Guide and this document are great resources on this subject.

Having said that, for this situation I don't think the error can be resolved by combining the contiguous RAM regions. Even if you were to combine all the RAM regions you would have only 0x17B0 total RAM available (adding up the lengths of all the RAM regions). Your .text section (code) alone is 0x15ba, so depending on the size of the other sections that are allocated to RAM (ramfuncs, .stack, .ebss, etc), all of these sections may still not fit into the RAM memory of this device. You could try enabling optimization in the project's Compiler options to see if that reduces the code size enough to make it fit within the available memory. Also take a look at the link map file which is generated by the project build, it will show you the size of the other sections. Using this information you may be able to tailor the linker command file to make the sections fit.

If code size is not sufficiently reduced by optimization, I would suggest that you consider programming the code to Flash instead of RAM. This will give you a lot more memory to work with. There are some extra considerations to take into account when programming to Flash. You could take a look at the Flash example included with ControlSuite and C2000Ware to help you get started.

Thanks for your quick reply . I'm trying with flash file but i'm not getting the exact output . I'm using adc soc program in control suite but i am not getting the correct values.The values are 1D,1E,1F,20,21 in the adc result registers.

I'm sorry I don't understand the issue. Are you saying that you converted the adc_soc example to run from Flash, as I believe the default runs fro RAM? Is it the out-of-box example or a modified version, as the out-of-box examples are pretty well tested and validated.

ADDAGUDURU SURYA KIRAN said:

I modified the adc soc program in control suite for my project and i also tested adc soc example in control suite with flash .Both of them are giving me wrong results .

This would be a question for the C2000 forum. The C2000 team creates and maintains the examples in ControlSuite/C2000Ware so they would be in the best position to answer this. We can answer CCS and tools questions in this forum but for this question about the expected results of the adc soc example, I would suggest that you start a new thread and post it to the C2000 forum.