CCS/AM3354: Compile error

zemin shan

Part Number: AM3354

Tool/software: Code Composer Studio

Hello

Since I use compiler the following code with CCS in LTS , I got error message "expect an }".

void CPUIntrEnable(uint32_t status)
{
    status = status & INTC_ARM_IRQ_FIQ_MASK;
    asm volatile (" mrs r0, CPSR\n\t"
                    " bic r0, r0, %[result]" : [result] "=r" (status));
    asm volatile (" msr CPSR, r0");
}

uint32_t CPUIntrDisable(void)
{
    volatile uint32_t status;

    /* Read the IRQ and FIQ status from CPSR */
    asm volatile ("    mrs     r0, CPSR\n\t"
                  "    mov     r1, r0\n\t"
                  "    and     %[result], r0, #0xC0" :
                              [result] "=r" (status));
    asm volatile ("    orr     r1, #0xC0\n\t"
                  "    msr     CPSR, r1");

    status = (~status) & INTC_ARM_IRQ_FIQ_MASK;
    return status;
}

So I decide to write the function CPUIntrEnable and CPUIntrDisable wiht assembler in an .s document,

but I do not know how to write, can you give an example, I need help.

Best Regards

Jack

over 5 years ago

0 zemin shan over 5 years ago

Intellectual 490 points

In addition

I try use intrinsics _enable_IRQ and _disable_IRQ, the program run to error

Best Regards

Jack

0 George Mock over 5 years ago

TI__Guru**** 251230 points

I presume you use the TI ARM compiler, and not any GCC ARM compiler. The TI ARM compiler supports an asm statement. But it is different and much simpler than the one supported by the typical GCC ARM compiler. It is no surprise the examples in your first post see this error ...

zemin shan said:
I got error message "expect an }".

Regarding ...

zemin shan said:

I decide to write the function CPUIntrEnable and CPUIntrDisable wiht assembler in an .s document,

but I do not know how to write, can you give an example, I need help.

I am not aware of any examples specifically prepared for this situation. Please search the TI ARM compiler manual for the sub-chapter titled Interfacing C and C++ With Assembly Language. General information on the assembler and assembly code is in the TI ARM assembly tools manual. The compiler installation includes the source to the RTS library, which has many assembly language source files. If you have CCS installed, look for files with the extension .asm in a directory path similar to ...

C:\ti\ccs1000\ccs\tools\compiler\ti-cgt-arm_20.2.0.LTS\lib\src

Thanks and regards,

-George

0 George Mock over 5 years ago in reply to zemin shan

TI__Guru**** 251230 points

zemin shan said:
I try use intrinsics _enable_IRQ and _disable_IRQ, the program run to error

That is too vague to act on. Please prepare a small example project that runs, then start a new thread in the forum for the specific processor you use.

Thanks and regards,

-George

0 zemin shan over 5 years ago in reply to George Mock

Intellectual 490 points

Hello George

Since I try replace the function CPUIntrEnable in an assembler function, the code will

enable clear CPSR's IRQ bit.

void CPUIntrEnable(uint32_t status)
{
     status = status & INTC_ARM_IRQ_FIQ_MASK;
     asm volatile ("    mrs     r0, CPSR");
     asm volatile ("    bic     r0, r0, %[result]" : [result] "=r" (status));
     asm volatile ("    msr     CPSR, r0");
}

CPUIntrEnable

    MRS     R0, CPSR                           ; Pickup current CPSR

    BIC     R0, R0, #0X80                      ; Clear interrupt lockout
                                                             ; bits in CPSR
    MSR     CPSR_cxsf, R0                   ; Setup new CPSR value
    MOV     pc, lr

I make a break point in statement MSR CPSR_cxsf, R0

I run the program in full speed and stopped in the break point, then I run the program in full speed again,

but the program run to error . It means after the bit 7 in CPSR is clear, the program run to error immediately.

It is really confused me a lot, we need you help to solve it.

Best Regards

Jack

0 Frank Livingston over 5 years ago in reply to zemin shan

TI__Mastermind 29778 points

Hi Jack,

The modification you've made to the code looks correct. From what I can see, you've simply replaced GCC syntax with LTS syntax.

If you don't enable IRQ interrupts, does your code crash?

Do the code ever arrive at an IRQ ISR once IRQ interrupts are enabled? I suggest you check whether the code arrives at any ISR, and check if the code in the ISRs is behaving correctly.

The TI ARM LTS compiler isn't supported for AM335x PRSDK, so you're on your own when it comes to transitioning from GCC to the TI ARM compiler.

Please see: https://software-dl.ti.com/processor-sdk-rtos/esd/docs/06_03_00_106/AM335X/rtos/index_release_specific.html#processor-sdk-v06-03-00

"The following compilers are bundled with the SDK installer"

Regards,
Frank

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CCS/AM3354: Compile error