Was looking at getting a HALCoGen based project for a RM48L952 Cortex-R4F compiling using ARM-CGT-CLANG-1_1.3.0-beta.1, by adding a new build configuration in CCS project which was originally set to use the TI ARM CGT v20.2.5 compiler.
The project uses an IRQ, and the main function contains the following intrinsic to enable IRQs:
/* Enable IRQ - Clear I flag in CPS register */
/* Note: This is usually done by the OS or in an svc dispatcher */
_enable_IRQ();
Which with the TI ARM CGT v20.2.5 compiler generates the following assembler as shown by the Disassembly view in the CCS debugger:
93 _enable_IRQ();
08001620: F1080080 cpsie i
When initially attempted to compile the sys_main.c source file with the ARM-CGT-CLANG-1_1.3.0-beta.1 compiler got the following informative error, as a result of -Werror=ti-intrinsics:
../source/sys_main.c:93:5: error: _enable_IRQ is a legacy TI intrinsic and is not supported in clang compilers [-Werror,-Wti-intrinsics]
_enable_IRQ();
^
Following Non-ACLE Compiler Intrinsics in the TI Arm Clang Compiler Tools User's Guide v1.3 #included ti_compatibility.h. That resolved the compiler error, but when ran the program no interrupt was serviced due to the I bit in the CPSR being set. The Disassembly view in the CCS debugger showed that no assembler was generated for the _enable_IRQ() call.
The C:\ti\ccs1030\ccs\tools\compiler\ti-cgt-armllvm_1.3.0-beta.1\include\c\ti_compatibility.h contains the following for _enable_IRQ() :
/******************************************************************************/
/* Enable IRQ status bit and return CPSR */
/******************************************************************************/
static __inline__ uint32_t __attribute__((always_inline))
_enable_IRQ(void)
{
#if __ARM_ARCH_PROFILE == 'M' && (__ARM_ARCH == 6 || __ARM_ARCH == 7)
uint32_t primask = __get_PRIMASK();
__asm volatile ("CPSIE I" : : : );
return primask;
#else
return 0;
#endif
}
The issue is that the static inline in ti_compatibility.h only generates code in _enable_IRQ() for Cortex-M profiles, and is a no-op for a Cortex-R profiles. This appears a bug since the TI ARM GCT _enable_IRQ() intrinsic does emit a "cpsie i" instruction for a Cortex-R profile. I haven't checked if other intrinsic replacements in ti_compatibility.h also have a similar issue of being no-ops on Cortex-R.
The CCS project is attached.
