CCSTUDIO-SITARA: Enabling DDR in CCS11

Lee Thalblum

Part Number: CCSTUDIO-SITARA

I'm trying to enable DDR on the TMDS64GPEVM. I've enabled it on CCS using SysConfig. When I try to debug I get the following messages:

MAIN_Cortex_R5_0_0: GEL Output: CPU reset (soft reset) has been issued through GEL.
MAIN_Cortex_R5_0_0: Trouble Writing Memory Block at 0xa4100000 on Page 0 of Length 0x1000: (Error -1065 @ 0xA4101000) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.5.0.00143)
MAIN_Cortex_R5_0_0: File Loader: Verification failed: Target failed to write 0xA4100000
MAIN_Cortex_R5_0_0: GEL: File: C:\Projects\fdic\fdic\Debug\fdic.out: Load failed.

I have several questions:

I've seen a reference to one or more script files that should be run. The scripts option in my Code Composer is empty. Where are the script files stored?

Address 0xa4100000 should be the beginning of DDR, but it should be considerably larger than 0x1000. Where is this value coming from?

Anything else relevant to enabling DDR.

Regards,

Lee Thalblum

over 2 years ago

0 Lee Thalblum over 2 years ago

Prodigy 100 points

Sorry, on second look, where is address 0xA4100000 coming from? That doesn't seem to be part of the Main domain memory map.

0 Rajat Batra over 2 years ago

TI__Intellectual 1155 points

Hi Lee,

In order to initialize the DDR memory you can follow the steps mentioned under Getting Started -> EVM Setup -> AM64X EVM -> Additional Details -> SOC Initialization ->SOC Initialization Using CCS scripting of the the MCU+ SDK manual available at dev.ti.com/.../node

Let me know if this resolves the issue.

Lee Thalblum said:
Address 0xa4100000 should be the beginning of DDR, but it should be considerably larger than 0x1000. Where is this value coming from?

Let me verify this and get back to you.

Regards

Rajat Batra

0 Lee Thalblum over 2 years ago in reply to Rajat Batra

Prodigy 100 points

Hi Rajat,

I looked at the DDR Initialization section of the document you referenced. It makes use of specific script files. As I mentioned in my original post, the Scripts menu selection of my CCS is empty. Where do I find the scripts that should be there?

Regards,

Lee

0 Rajat Batra over 2 years ago in reply to Lee Thalblum

TI__Intellectual 1155 points

Hi Lee,

As mentioned in the section (SOC Initialization Using CCS scripting -> Set Environment Variable) of the above mentioned document you need to add the root path of the MCU+ SDK to your environment variable and then CCS should be able to pick up the scripts.

Do note that scripts will only show up under scripts menu once you connect debugger to cortex R5 as mentioned in the section (SOC Initialization Using CCS scripting -> Run the SOC Initialization script)

Regards

0 Lee Thalblum over 2 years ago in reply to Rajat Batra

Prodigy 100 points

Hi Rajat,

This seems to have resolved the issue. I can now load and debug. Thanks for your help.

Regards,

Lee

0 Lee Thalblum over 2 years ago in reply to Lee Thalblum

Prodigy 100 points

Quick followup question: Where does the configuration information that's contained in the scripts come from in the final release code? Is that added to the generated code from syscfg during a release build, or is it not needed for a final release build?

+1 Rajat Batra over 2 years ago in reply to Lee Thalblum

TI__Intellectual 1155 points

Hi,

In production release the SBL should initialize DDR before loading application images.

Regards

Rajat

0 Lee Thalblum over 2 years ago in reply to Rajat Batra

Prodigy 100 points

Hi Rajat,

Thanks for the response.

Regards,

Lee

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CCSTUDIO-SITARA: Enabling DDR in CCS11