JTAG link (XDS110) with SK-TDA4VM trough CCS 12.10

Hi Mickaël,

As a warning, SK-TDA4VM does not have an on-board debugger, so an external debugger will need to be bought. There is a FAQ for XDS560v2 that I recently created that can be used to reference the general flow of setting up CCS with an external debugger: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1178240/faq-sk-tda4vm-how-do-i-connect-the-external-debugger-blackhawk-usb560v2-xds560v2-usb-system-trace-to-the-board?tisearch=e2e-sitesearch&keymatch=faq%2520sk-tda4vm#

Although the device is slightly different, the screenshots from the FAQ can be used as a reference for what the expected screen should be at each step of setting up. Please see if this helps in finding out what the issue could be. If the issue persists, please send me a screenshot of the error messages you are seeing.

Regards,

Takuma

Hi Takuma,

Thank you for your feedback which has been very useful to me.

I have advised you to buy a TMDSEMU560V2STM-UE probe from Farnell (few suppliers can supply this type of probe at the moment). Well, it's not a blackhawk but a Spectrum Digital.

I was able to see under CCS12.1 on my SK-TDA4VM card but only when I'm in boot mode on the SD... If I put myself in "no boot" mode then the probe can't see the resources... However, I would like to be able to target only ke C7x and, if I correctly understood the idea contained in all the TI docs, it must be put in this mode. Then when we see under CCS all the resources, then we can connect the resource that we want to load an executable.

Is it this ?

Hi Mickaël,

 I have not tried out the "no boot" mode yet, but the general flow should be similar to the flow for the EVM board: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_05_00_11/exports/docs/psdk_rtos/docs/user_guide/ccs_setup_j721e.html

In the EVM flow, there is a GEL file that needs to be set in the target configuration file, as well as a javascript script that needs to run to initialize the cores, which is different from booting up from SD card.

Could you try this out?

Regards,

Takuma

Hi Takuma,

It seems that de GEL fil is only for R5 in lock step mode. I want to use C7x_0... So where can i found GEL file for C7x ?

Thanks,

Mickaël

Hi Mickaël,

Apologies for the delayed response. I just got back from a business trip and need some time to handle various tasks. I will be able to experiment around with the GEL file next week.

In the meantime, there should be a .gel file named J721E.gel (not J721E_R5LOCKSTEP.gel) which configures the C71x_0. Can you confirm that the following file is loaded into DMSC: ${CCS_INSTALL_PATH}/ccs_base/emulation/gel/J721E_DRA829_TDA4VM/gel/J721E.gel

Combined with the launch.js also mentioned in the userguide I linked in my previous post, this should initialize the C66x, C71x, and R5F cores, as well as DDR, such that you can connect to the C71x and load in any binaries compiled for the C71x.

Regards,

Takuma

Hi Takuma,

Thanks for the redirection, indeed, my subject is related to this thread.

We finally get to move on, we just had to specify the memory map in a .cmd file and add it in the compiler linker.
We successfully ran our test example (printf and basics other tests) but we encountered a new problem when trying to read from the DDR.

According to the GEL file J721E_DDR32SS/J7_DDR_config.gel, the DDR Base seems to start at address 0x82990000. We saw different sections like the DDR controller, the DDR PI etc.
At what address can we start using it ? We tried many differents addresses but each time it resulted in the following error :

C71X_0: Trouble Writing Memory Block at ... (Error -1348 - (678:16:188)) Register or Memory request has timed out.
C71X_0: Trouble Reading Memory Block at ... (Error -1348 - (0:0:0)) Register or Memory request has timed out.

Hi Tim,

Here is documentation about the memory map that is used by our SDK: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_05_00_11/exports/docs/psdk_rtos/docs/user_guide/developer_notes_memory_map.html

The documentation also explains how to use a tool that constructs the memory map, so I would recommend going through this.

Regards,

Takuma

Hi Takuma,

(An addition to what my colleague Tim requested)

It was forgotten to specify that we directly address the C7x without OS. We manage to load a program into the L2 or the SRAM of the MSMC. on the other hand, when we try to address the DDR to put our .const section, then we have the error on the address of the DDR where this section must be put (0xAA604000, DDR_C7X_1 in the linker_meme_map.cmd file).
It's as if we were missing a configuration of the MSMC or the DDRSS. Would there be something to specify in the .GEL or .js file (Javascript) or other?

We have already followed the documentation on the memory map that you specified. Generated the linker_mem_map.cmd file, which we try to complete with the SECTION part to specify that we want to put our weights in the DDR...
Thanks for your help.

Can you give us the memory map for the C7x of the SK-TDA4VM ? is it the same of the J721E ?

Thanks,

Mickaël

Hi Mickaël,

Attached is the app_mem_map.h that is used by the OS and example applications we have for SK-TDA4VM:

app_mem_map.h

For no OS, are the DIP switches set for no boot mode? It should be in the position specified in 2.2.1 in the SK board's userguide: https://www.ti.com/lit/ug/spruj21c/spruj21c.pdf?ts=1674507938359

Regards,

Takuma

Hi Takuma,

Thanks you for the app_mem_map.h.  I will change my linker.cmd file with the good address for the DDR and test this.

For the second point...

Yes the sk-tda4vm is in "no boot mode" (switch 1 to SW1.1=On, SW1.2=OFF, SW1.3=OFF)

Another question : How to extend the memory map of the C7x : switch from 32-bit to 64-bit address (obviously all this is baremetal) ?

Regards

Mickaël

Hi Takuma,

We changed the memory map, but that does not change our problem. We still can't access the DDR from the C7x.
I wonder if you don't have the header and source files for the SK-TDA4VM card. It looks like we should use the following files attached to this platform:
board/src/sk-tda4vm/include/
                                             board_cfg.h
                                             board_clock.h
                                             board_control.h
                                             board_ddr.h...
board/src/sk-tda4vm/
                                             board_clock.c
                                             board_control.c
                                             board_ddr.c...
                                              board_cfg.h
                                              board_clock.h
                                              board_control.h...

This repository tree exists for the j721e... can you give us these file for the SK-TDA4VM or isiti possible to modify those for the J721e board ?

Thanks,

Mickaël

Hi Takuma,

Thank you for supporting our customer. As they report that the C7x DSP cannot yet access the DDR memory, they are wondering whether some more modules like SMMU or others need to be configured. Do you you have an example for that?

Best regards,
François.

Hi Takuma,

We finally succeded in accessing the DDR memory from the C7x.

It turned out the issue was in the linker file, as the sizes of the heap and stack given were too large to fit. (We are not sure that it is the exact reason though, anyway it works now)

Anyway, if you could send us documentation about the SK-TDA4VM it would certainly help us for the continuation of our project. 

Thank you for your support,

Best regards,
Axel

Hi Axel,

Which SK-TDA4VM documentation are you referring to? Please specify which information you are missing.

Best regards,
François.