Spent 3 days to wonder was loosing my mind but managed to work around ADC registers source stepping F5/F6 all appear cross wired in debug however behave correctly on the peripheral when disconnected from JTAG.
Also had numerous crashes (Win7 program stop responding message) during debug load program flash. Crashes occur after changing computer IP address and not allow Eclipse firewall access to internet. Expecting to change the IP back when finished, why modify the firewall tables adding a static IP address bound to the NIC (security risk). Sharing data in the same computer memory space as debug and Ethernet console GUI, the target was running allowing verify & clear fault condition and test ADC measured analog voltage values set properly. Ended up having to trial and error low/high conversion values, PANIC was easily tripped during the FOC ramp velocity.
Has the ADC register status flags been fixed in CCS5.5 or has anyone else see this behavior?
Cross posted code and issue verified in Stellaris forum.