AM572x IPU reset failure using Emulation probes

The AM57x team have been notified. They will respond here.

Don,

Apologies for the delayed response. Are you still encountering this problem?

Lali

Lali,

Yes, we have not identified a way to reset/release the M4 cores.

thanks

--Don

Don,

You are doing a warm reset on IPU1?

If so, is the sequence for a warm reset outlined in section 3.5.6.11 IPU1 Subsystem Software Warm Reset Sequence of http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf followed?

Lali

Lali,

> You are doing a warm reset on IPU1?

That is correct.

> If so, is the sequence for a warm reset outlined in section 3.5.6.11 IPU1 Subsystem Software Warm Reset Sequence of www.ti.com/.../spruhz6h.pdf followed?

I have read that section of the TRM. It describes how to drive the IPU1 warm reset from one of the A15s. I am trying to drive the reset using a JTAG probe. My goal is to reset IPU1 via the JTAG probe without touching the MPU/A15s, and leave IPU1 suspended and ready for debugging. So I have adapted the procedure slightly in order to do accomplish this goal. Presumably Code Composer Studio does something similar. I have tried a number of variations on this procedure; this one is my best guess.

In the pseudo-code shown in my original posting, the line with the comment "Assert reset for IPU1 (MMU/Unicache, Core0, Core1)" accomplishes steps 1 and 2 from the TRM reset sequence. I have tried enabling IPU1_GFCLK after this (i.e. part of step 4), but it has had no effect.

The line in the pseudo-code with the comment "Deassert reset for IPU1 MMU/Unicache" accomplishes the remainder of step 4 and step 6.

Steps 3 and 5 don't appear to require any action.

I have done experiments to determine that the pre-requisites are met (IPU CPUs idle, clock gated) before attempting reset. Also, when initializing the ICEPick after connecting to the board I have set wait-in-reset mode for both of the IPU1 M4 cores.

I look forward to your suggestions.
Thanks,
--Don

Don,

To isolate the issue, could you please verify that you can perform this operation with CCS via XDS200 or XDS560v2?

Lali

Lali,

I have set up an XDS200 with an AM572x and tried to connect to and debug a bare-metal M4 application without first connecting to one of the A15s.  So far I have not been successful.

The procedure I followed was this:

• I first connected to and debugged on the M4 using the procedure outlined here:
  • http://processors.wiki.ti.com/index.php/Processor_SDK_Bare_Metal_Examples#ARM_Coretex-M4
  • This involved connecting to the A15 first.  This approach works fine.
• I then tried to modify the target configuration so that I wouldn't have to connect to the A15 first
  
  • set the A15, C66xx, and ARM9_ICONTn components to "bypass"
  • deleted/commented out sections of a number of the gel files to eliminate code that doesn't apply to M4 debug sessions, e.g. DDR init.
  • change the initialization script for Cortex_M4_IPU1_C0 to gpevm_am572x.gel
  • copy the contents of the Startup and OnTargetConnect functions from AM572x_coretexM4_startup.gel into the corresponding functions in gpevm_am572x.gel.
• Launch the target configuration as usual, and try to connect to M4_IPU1_C0

The results were as follows:

Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset, value 0x25000003.
CS_DAP_IPU_1_C0: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_IPU_1_C0: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_IPU_1_C0: GEL Output: DEBUGSS DPLL is not locked, time out occured  
CS_DAP_IPU_1_C0: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_IPU_1_C0: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_IPU_1_C0: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_IPU_1_C0: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_IPU_1_C0: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_IPU_1_C0: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_IPU_1_C0: GEL Output: --->>> Applying Firewall Settings... <<<---
CS_DAP_IPU_1_C0: GEL Output:     --->>> TEST device, FW settings needed -> allow all access <<<---
CS_DAP_IPU_1_C0: GEL Output: --->>> Firewall Settings DONE! <<<---
Cortex_M4_IPU1_C0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.504.1)

Note that I've tried a number of variations on this approach, with generally similar results.

Questions:

1. Should I be able to connect to and debug on an M4 without first connecting to an A15?
2. If so, is the approach above on the right track? 
   1. how can I resolve the error?
   2. If it's not the right approach, what should I be doing differently?
3. If it is a requirement to first connect to the A15, would you please explain the reason why?

Thanks

--Don

Don,

I'm checking with some folks internally and will post back here once I have a response.

Lali

You do not have to connect to a Cortex A15 to configure and release the Cortex M4 cores.  You will however need to access system memory to do the configuration, and that will require you connect to the Cortex A15 DAP (CS_DAP_DebugSS).  But you can do that without needing to connect the Cortex A15.  Until properly configured and released from reset, you will not be able to access the Cortex M4s or their DAPs.

The following link is for a GEL file that will enable debug on the Cortex M4s.  This is taken from the GEL files for the device and stripped down to what I think would be close to the minimum steps necessary to do this. Launch your configuration (make sure the CS_DAP_DebugSS isn't marked as BYPASS).  Right click in the Debug view and select "Show all cores."  Find the CS_DAP_DebugSS under Non-debuggable devices, and connect to it.  Choose menu item Tools -> GEL Files, and in that window right-click and select "Load GEL.."  Load the file from the link below.  Under the Scripts menu you'll now find a default->ReleaseIPUs option. Run that and you should then be able to connect to all of the Cortex M4s.

/cfs-file/__key/communityserver-discussions-components-files/81/releaseIPUs.gel

This was tested using an AM572x IDK EVM.  There is different code needed for the GP EVM, but that's in the comments in the GEL script. Some of the MMU setup may not be required, but I left it in.

This GEL file worked for me with my AM572x GP EVM (after tweaking for the GP-specific code).  I should be able to make some progress using this.

Thanks!

--Don

Another question wrt this: In AM572x_dap_startup.gel, function dpll_dbgss_config_board is called by OnTargetConnect. In that function there are statements like this one:

DEBUGSS_CFGBUS_PLLCTRL_PLL_CONFIGURATION1@data = 0x2483B612 ;

which writes to address 0x8003180C, according to the #defines in that file. What is that address, and how can it be accessed? I haven't found any explanation of the Debug Subsytem DPLL in the AM572x TRM, nor any references to that address. Can you clarify, and/or point me to the appropriate documentation?
Thanks
--Don

Don,

Sorry for the slow reply to your question. Could you please close this thread and re-open another for your question on the AM572x_dap_startup.gel ?

This will ensure it will get assigned correctly. Thanks.

Lali