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CCS/CCSTUDIO-KEYSTONE: EDMA doesn't work when I reload DSP code in CCS

Part Number: CCSTUDIO-KEYSTONE

Tool/software: Code Composer Studio

My project is using Keystone DSP 66AK2H06 and XDS560V2 USB emulator. When I do hardware reset, after Linux boot up, I load DSP in CCS window and click run, DSP runs OK. EDMA data transfer from FPGA to DSP L2 memory works good. But if I reload DSP in CCS window and click run, DSP runs but EMDA data transfer stops. Sometimes I got the following error message when I reload the DSP code. What do I missing in the code configuration?

Thanks

Mike

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  • Mike,

    >>But if I reload DSP in CCS window and click run, DSP runs but EMDA data transfer stops.
    Despite I don't know how your application is configured, the initialization procedure is important: reload/restart does not reset the board/device. It mostly places the PC at the entry point of your code. In this case, any peripheral/interrupt that is pre-configured from a previous run may get in the way of the regular code execution and disrupt the normal flow. That may be happening either inside the device (the EDMA or initialization code are relying on a default/reset register value) or externally (the FPGA may be hung expecting a specific sequence of data that is not properly sent).

    >>Sometimes I got the following error message when I reload the DSP code. What do I missing in the code configuration?
    An explanation for the error is shown at section 5.7 of the page below:
    processors.wiki.ti.com/.../Debugging_JTAG_Connectivity_Problems

    As the reference mentions, the configuration itself is fine but the hung core partially validates my previous suggestions: the device may be waiting for an external resource (FPGA) to be ready that is also waiting on the DSP to be ready - a hang condition.

    Unfortunately in these cases it is difficult to provide any direct suggestions as they are heavily dependent on the application itself. However, I would carefully inspect the EDMA registers when they come straight from reset and compare with their status after a reload (you can right-click on the registers view and export to a .txt file). I would also inspect the FPGA status after a board reset and after a code reload - if the FPGA is mapped to the device memory, you can save its contents as shown in the reference below:
    processors.wiki.ti.com/.../GSG:Debugging_projects_v5

    Hope this helps,
    Rafael
  • Thanks for the support. It seems it works if I reset CPU from the CCS before I reload the DSP code