• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 54 subscribers
  • Views 1455 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/CCSTUDIO-KEYSTONE: ARM and DSP read different value from the same MSMC location

Mike Chen
Prodigy 100 points

Part Number: CCSTUDIO-KEYSTONE

Tool/software: Code Composer Studio

Hi,

We are using MSMC memory as the dual port memory between ARM and DSP communication. DSP keeps writing the data to one location in MSMC (for example, location 0xc000140). From the CCS memory browser, I can see the value keep change in location 0xc000140. But in the ARM side, I used devmem2 to read 0xc000140 location, the value doesn't change. I stopped the DSP, the value still doesn't change. But if I manually changed the value on 0xc000140, then I can read the collect value from the ARM side.

The question is what can affect the MSMC memory read from the ARM side? Why DSP and ARM can read different data from the same memory location?

Thanks

Mike

  • 0
    TI__Guru**** 420930 points
    Hi Mike,
    Please provide the device and full CCS version that you are using.

    Thank you
    ki
  • 0 in reply to Ki
    Prodigy 100 points
    The CCS version is 6.1.3.00034, the device is 66AK2H06, the emulator is XDS560V2 STM USB
  • 0
    Guru 92251 points

    Mike Chen10 said:
    The question is what can affect the MSMC memory read from the ARM side? Why DSP and ARM can read different data from the same memory location?

    Is the MSMC memory considered cacheable by the ARM and/or DSP?

    From memory, on the Keystone II devices only the ARM supports hardware cache snooping and the DSP requires software handling of cache coherency.

    When using the CCS memory browser selecting the "CPU Memory View" shows the values as seen by the CPU cache, and the "Physical Memory View" shows the value in the physical RAM. If the "CPU Memory View" and "Physical Memory View" have different values that could point to a cache coherency issue (or the MMU is performing a translation).

  • 0 in reply to Chester Gillon
    Prodigy 100 points
    Both DSP and ARM will not consider MSMC as cacheable memory. We will use it as dual port memory to transfer data between DSP and ARM.
    I have tried your suggestion. from CPU memory view, I can see the data change, from Physical memory view, I can't see the data change. So it is cache coherency issue as you pointed out.
    How can I avoid this cache coherency issue? change my data address to other location of MSMC? Add MSMC configuration code for DSP and ARM?

    Thanks
    Mike
  • 0 in reply to Mike Chen
    Guru 92251 points

    Mike Chen10 said:
    How can I avoid this cache coherency issue?

    Looking at the Inter‐Processor Communications (IPC) HeamMemMP and ListMP modules from ti-processor-sdk-rtos-k2hk-evm-02.00.02.11 the Cache_inv() and Cache_wbInv() functions are used to manage the cache coherency.

    I don' know what software you are running, e.g. bare-metal, RTOS or Linux, but there might be an existing IPC mechanism you could use.

    I haven't yet attempted to perform IPC on Keystone II devices, you will get a better answer by asking the device experts on the Keystone Multicore Forum (C66, 66A, AM5, TCI)