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CCS/TMS320F2808: TMS320F2808

Part Number: TMS320F2808
Other Parts Discussed in Thread: C2000WARE, CCSTUDIO, SPRC191

Tool/software: Code Composer Studio

I am getting started to program a processor board with TMS320F2808.

I am using Code Composer Studio 8  and and emulator XDS200. The communication of the hardware with CCS seems to work.

I want to begin with examples downloaded from

I want to proceed exactly according to the related document   "DSP280x_HeaderFiles_QuickStart_Readme.pdf"

I am at the page 6 of the document and I am trying to execute the step A.  I want to execute Load GEL command from File menu.

The command does not exist in the File menu. I execute the steps B and C opening the file. I want to continue executing the step D.

I cannot find the pull down menu containing the command Load_and_Build_Project.

Because the Code Composer Studio does not behave as described I am completely impotent to get started.

Please tell me what is wrong in the document   "DSP280x_HeaderFiles_QuickStart_Readme.pdf" or what mistake I have done

and tell me how can I click step by step to run an example from the collection, for example GPIO program with GPIO pins oscillating?

My email address is following        <>

  • The document you are referring to was written for CCSv3.x. The CCS version you are using (v8) is considerably different compared to 3.x. CCS3.x is not supported any more. The F2808, being a relatively old device in our portfolio, is not supported on C2000ware. You have two options:

    1. Move to a newer device, so that you get the benefit of seamless support in C2000ware. Meaning, you can come up to speed quickly with the examples provided in C2000ware.

    2. You can still run the examples provided in the DSP Header files. However, you cannot use the procedure outlined in the Readme doc. You must use the Project-->Import Legacy CCS3.3 project option. This allows you to import .PJT files from CCS3.x projects.

  • Peter,

    In addition to the reply from Hareesh, to help you learn more about the C2000 MCUs please see our hands-on workshops at:

    (Please note that there is an archive section for older processors, too).

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • Peter – I haven’t heard back from you. I’m assuming your concerns have been addressed. If not, just post a reply below.
  • Dear Friend, Mr. Hareesh,

    you recommended me to use in CCS 8 the command  Project => Import Legcy CCSv3.3 Projects.

    After I imported the file .pjt" and clicked Next => Finish,

    I obtained following error message

    Issues that may require your attention were encountered while migrating the

    project(s). Please see the 'project.log' file, in the root of each project, for details.

    The log file contains (Censored! Please refrain from using expletive words) that cannot help me:

    !CONFIGURATION: 'com.ti.ccstudio.buildDefinitions.C2000.Release.1114035985' [Thu Jan 24 17:47:11 CET 2019]

     !TOOL: 'com.ti.ccstudio.buildDefinitions.C2000_18.1.exe.compilerRelease.1623379253'

      !WARNING: Unresolved option: com.ti.ccstudio.buildDefinitions.C2000_18.1.exe.compilerRelease.1623379253::!--symdebug:dwarf

  • my issue was not resolved because the recommended proceeding in CCS caused error messages.
  • Peter,
    It would be better if you learn how to create a project from scratch, rather than trying to import an already existing .pjt file (which is compatible only with CCS3.3) into the CCS8 framework. Creating a new project from scratch is covered in all workshops. Ideally, you should follow the ‘CCS’ directions for the F28379D workshop since it uses CCSv7. The directions for lab 2 show how to create a new project, and the directions from lab 5 shows how to add the header files. I hope this helps.

    Note that even though the workshop is targeted towards a different device than what you are using, the process of creating a project is the same.
  • Dear Firend, Mr. Hareesh,

    I have no problem to create a new project and scratch necessary code from existing examples.
    I can create a new CCS projet including correct settings without problem.

    My problem is that I created a trivial program that only disables the Watchdog, sets the GPIO port to output mode
    and changes the state of the GPIO pins. After I build the project and load to RAM memory (debug command)
    and I try to to run the program the processor starts generating signals at the SPIA interface like in the SPIA boot mode.
    However, the processor had not to jump into SPIA boot mode because the emulator is due to override the boot mode
    and in addition my hardware setting of boot mode is (1,1,1) = Boot to Flash.
    I tried to run the program in step mode. It does not do anything, the GPIO signals do not work.
    However, if I put into my program statements to write data into a RAM memory location, it works in step mode only.
    That is why I am not sure that my program is correct and tried to import a 100% correct example.
    As soon I will create my first functional program I will be able to create any program. I have 35 years experience
    in microprocessor programming. I made my first excellent industry programs in 1983 with uP INTEL 8080.
    The only effective help for me is if somebody would look at my screen by Team Viewer and would see the behavior
    of the CCS8 that does not work properly.

  • Peter,

                I don’t know which GPIO pins you tried to toggle, but could it be that the GPIO pins you tried to toggle are multiplexed with the SPI function? (Please look at Table 4-16 of SPRS230N for muxing options). 

    Did you try Example_280xGpioToggle.c in C:\tidcs\c28\DSP280x\v160\DSP280x_examples\gpio_toggle directory? This is a tested code and should work "as is". Else you can use the attached code, which is just a few lines. 

    What hardware are you using? Is it your own board? 

    Teamviewer is blocked by our network; I cannot use it.

    #include "DSP280x_Device.h"
    asm("  EALLOW");
    /* Disable Watchdog  */
        SysCtrlRegs.WDCR = 0x006F;    
    /* Configure GPIO pin */
    	GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
    	GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;	
    /* Toggle GPIO pin */
    	GpioDataRegs.GPATOGGLE.bit.GPIO0 = 1;

  • Dear Friend, Mr. Hareesh,

    I tried to run the code send by you. There are two problems.

    1. When building the project, the compiler cannot find the header files.
       I have installed header files from the SPRC191 file downloaded from internet.
       The installer created the header files structure exactly according to the official document
       "DSP280x_HeaderFiles_QuickStart_Readme.pdf", they are in "C:\tidcs" directory.
       However, the Code Compose Studio cannot find the header files.
       I have copied the "DSP280x_Device.h" into the project directory in my work space.
       The compiler could not find additional header files included in "DSP280x_Device.h".
       If I copy all required header files into my project directory, still the compiler
       cannot build the project because the important structures are defined as external:

       extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
       extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
       extern volatile struct GPIO_DATA_REGS GpioDataRegs;

       I can correct the mistake deleting the word "extern" and the project can be built.
       Because of many problems I made my own single header file "GPIO_Example.h"
       extracting only useful definitions from all header files. You can see it below at the end.
       I solved the problem by non standard method. Please tell me what mistake I have done
       that the Code Composer Studio cannot find the header files and the compiler
       tells that the structures are not defined and I had to correct mistakes in header files.

    2. The second problem is the real problem that I cannot solve.
       I had to make changes in the code sent by you, I replaced the "DSP280x_Device.h"
       by my own header file "GPIO_Example.h".
       I can build the project, to load it into RAM memory and to run it.
       I discovered that after I run the program, the processor jumps into SPI boot mode.
       This behavior does not depend at all on the program code in the "main.c" file.
       By oscilloscope I can see at the four pins of SPIA interface typical behavior

    of clock, data and control signals exactly corresponding to SPI boot mode.

    I have a professional processor board from a frequency converter for induction motors

    having a connector for an emulator.
    I have a complete scheme of the board forbidden to publish, and it is evident that all boot mode
    pins have pull up resistors resulting in 111 boot mode (Boot to Flash).
    I cannot understand the reason why the processor jumps into SPI boot mode
    regardless of what program I write.

    I think that you cannot find answer to this problem.
    I am asking you to send me answer at least to my header files problem No 1.

    This is my own header file code

    typedef unsigned int    Uint16;
    typedef unsigned long   Uint32;

    struct GPACTRL_BITS {        // bits   description
       Uint16 QUALPRD0:8;        // 7:0    Qual period
       Uint16 QUALPRD1:8;        // 15:8   Qual period
       Uint16 QUALPRD2:8;        // 23:16  Qual period
       Uint16 QUALPRD3:8;        // 31:24  Qual period

    union GPACTRL_REG {
       Uint32              all;
       struct GPACTRL_BITS bit;

    struct GPBCTRL_BITS {        // bits   description
       Uint16 QUALPRD0:8;        // 7:0    Qual period
       Uint16 rsvd1:8;           // 15:8   reserved
       Uint16 rsvd2:16;          // 31:16  reserved

    union GPBCTRL_REG {
       Uint32              all;
       struct GPBCTRL_BITS bit;

    struct GPA1_BITS {            // bits   description
       Uint16 GPIO0:2;            // 1:0    GPIO0
       Uint16 GPIO1:2;            // 3:2    GPIO1
       Uint16 GPIO2:2;            // 5:4    GPIO2
       Uint16 GPIO3:2;            // 7:6    GPIO3
       Uint16 GPIO4:2;            // 9:8    GPIO4
       Uint16 GPIO5:2;            // 11:10  GPIO5
       Uint16 GPIO6:2;            // 13:12  GPIO6
       Uint16 GPIO7:2;            // 15:14  GPIO7
       Uint16 GPIO8:2;            // 17:16  GPIO8
       Uint16 GPIO9:2;            // 19:18  GPIO9
       Uint16 GPIO10:2;           // 21:20  GPIO10
       Uint16 GPIO11:2;           // 23:22  GPIO11
       Uint16 GPIO12:2;           // 25:24  GPIO12
       Uint16 GPIO13:2;           // 27:26  GPIO13
       Uint16 GPIO14:2;           // 29:28  GPIO14
       Uint16 GPIO15:2;           // 31:30  GPIO15

    struct GPA2_BITS {            // bits   description
       Uint16 GPIO16:2;           // 1:0    GPIO16
       Uint16 GPIO17:2;           // 3:2    GPIO17
       Uint16 GPIO18:2;           // 5:4    GPIO18
       Uint16 GPIO19:2;           // 7:6    GPIO19
       Uint16 GPIO20:2;           // 9:8    GPIO20
       Uint16 GPIO21:2;           // 11:10  GPIO21
       Uint16 GPIO22:2;           // 13:12  GPIO22
       Uint16 GPIO23:2;           // 15:14  GPIO23
       Uint16 GPIO24:2;           // 17:16  GPIO24
       Uint16 GPIO25:2;           // 19:18  GPIO25
       Uint16 GPIO26:2;           // 21:20  GPIO26
       Uint16 GPIO27:2;           // 23:22  GPIO27
       Uint16 GPIO28:2;           // 25:24  GPIO28
       Uint16 GPIO29:2;           // 27:26  GPIO29
       Uint16 GPIO30:2;           // 29:28  GPIO30
       Uint16 GPIO31:2;           // 31:30  GPIO31

    struct GPB1_BITS {            // bits   description
       Uint16 GPIO32:2;           // 1:0    GPIO32
       Uint16 GPIO33:2;           // 3:2    GPIO33
       Uint16 GPIO34:2;           // 5:4    GPIO34
       Uint16 rsvd1:2;            // 7:6    reserved
       Uint16 rsvd2:8;            // 15:8   reserved
       Uint16 rsvd3:16;           // 31:16  reserved

    struct GPB2_BITS  {           // bits   description
       Uint16 rsvd1:16;           // 15:0   reserved
       Uint16 rsvd2:16;           // 31:16  reserved

    union GPA1_REG {
       Uint32              all;
       struct GPA1_BITS    bit;

    union GPA2_REG {
       Uint32              all;
       struct GPA2_BITS    bit;

    union GPB1_REG {
       Uint32              all;
       struct GPB1_BITS    bit;

    union GPB2_REG {
       Uint32              all;
       struct GPB2_BITS    bit;

    struct GPADAT_BITS {          // bits   description
       Uint16 GPIO0:1;            // 0      GPIO0
       Uint16 GPIO1:1;            // 1      GPIO1
       Uint16 GPIO2:1;            // 2      GPIO2
       Uint16 GPIO3:1;            // 3      GPIO3
       Uint16 GPIO4:1;            // 4      GPIO4
       Uint16 GPIO5:1;            // 5      GPIO5
       Uint16 GPIO6:1;            // 6      GPIO6
       Uint16 GPIO7:1;            // 7      GPIO7
       Uint16 GPIO8:1;            // 8      GPIO8
       Uint16 GPIO9:1;            // 9      GPIO9
       Uint16 GPIO10:1;           // 10     GPIO10
       Uint16 GPIO11:1;           // 11     GPIO11
       Uint16 GPIO12:1;           // 12     GPIO12
       Uint16 GPIO13:1;           // 13     GPIO13
       Uint16 GPIO14:1;           // 14     GPIO14
       Uint16 GPIO15:1;           // 15     GPIO15
       Uint16 GPIO16:1;           // 16     GPIO16
       Uint16 GPIO17:1;           // 17     GPIO17
       Uint16 GPIO18:1;           // 18     GPIO18
       Uint16 GPIO19:1;           // 19     GPIO19
       Uint16 GPIO20:1;           // 20     GPIO20
       Uint16 GPIO21:1;           // 21     GPIO21
       Uint16 GPIO22:1;           // 22     GPIO22
       Uint16 GPIO23:1;           // 23     GPIO23
       Uint16 GPIO24:1;           // 24     GPIO24
       Uint16 GPIO25:1;           // 25     GPIO25
       Uint16 GPIO26:1;           // 26     GPIO26
       Uint16 GPIO27:1;           // 27     GPIO27
       Uint16 GPIO28:1;           // 28     GPIO28
       Uint16 GPIO29:1;           // 29     GPIO29
       Uint16 GPIO30:1;           // 30     GPIO30
       Uint16 GPIO31:1;           // 31     GPIO31

    struct GPBDAT_BITS {          // bits   description
       Uint16 GPIO32:1;           // 0      GPIO32
       Uint16 GPIO33:1;           // 1      GPIO33
       Uint16 GPIO34:1;           // 2      GPIO34
       Uint16 rsvd1:13;           // 15:3   reserved
       Uint16 rsvd2:16;           // 31:16  reserved

    union GPADAT_REG {
       Uint32              all;
       struct GPADAT_BITS  bit;

    union GPBDAT_REG {
       Uint32              all;
       struct GPBDAT_BITS  bit;

    struct GPBPUD_BITS {          // bits   description
       Uint16 GPIO32:1;           // 0      GPIO32
       Uint16 GPIO33:1;           // 1      GPIO33
       Uint16 GPIO34:1;           // 2      GPIO34
       Uint16 GPIO35:1;           // 3      GPIO35
       Uint16 rsvd1:12;           // 15:4   reserved
       Uint16 rsvd2:16;           // 31:16  reserved

    union GPBPUD_REG {
       Uint32              all;
       struct GPBPUD_BITS  bit;

    struct GPIOXINT_BITS {        // bits   description
        Uint16 GPIOSEL:5;         // 4:0    Select GPIO interrupt input source
        Uint16 rsvd1:11;          // 15:5   reserved

    union GPIOXINT_REG {
       Uint16                all;
       struct GPIOXINT_BITS  bit;

    struct GPIO_CTRL_REGS {
       union  GPACTRL_REG  GPACTRL;   // GPIO A Control Register (GPIO0 to 31)
       union  GPA1_REG     GPAQSEL1;  // GPIO A Qualifier Select 1 Register (GPIO0 to 15)
       union  GPA2_REG     GPAQSEL2;  // GPIO A Qualifier Select 2 Register (GPIO16 to 31)
       union  GPA1_REG     GPAMUX1;   // GPIO A Mux 1 Register (GPIO0 to 15)
       union  GPA2_REG     GPAMUX2;   // GPIO A Mux 2 Register (GPIO16 to 31)
       union  GPADAT_REG   GPADIR;    // GPIO A Direction Register (GPIO0 to 31)
       union  GPADAT_REG   GPAPUD;    // GPIO A Pull Up Disable Register (GPIO0 to 31)
       Uint32              rsvd1;
       union  GPBCTRL_REG  GPBCTRL;   // GPIO B Control Register (GPIO32 to 63)
       union  GPB1_REG     GPBQSEL1;  // GPIO B Qualifier Select 1 Register (GPIO32 to 47)
       union  GPB2_REG     GPBQSEL2;  // GPIO B Qualifier Select 2 Register (GPIO48 to 63)
       union  GPB1_REG     GPBMUX1;   // GPIO B Mux 1 Register (GPIO32 to 47)
       union  GPB2_REG     GPBMUX2;   // GPIO B Mux 2 Register (GPIO48 to 63)
       union  GPBDAT_REG   GPBDIR;    // GPIO B Direction Register (GPIO32 to 63)
       union  GPBPUD_REG   GPBPUD;    // GPIO B Pull Up Disable Register (GPIO32 to 63)
       Uint16              rsvd2[33];

    struct GPIO_DATA_REGS {
       union  GPADAT_REG       GPADAT;       // GPIO Data Register (GPIO0 to 31)
       union  GPADAT_REG       GPASET;       // GPIO Data Set Register (GPIO0 to 31)
       union  GPADAT_REG       GPACLEAR;     // GPIO Data Clear Register (GPIO0 to 31)
       union  GPADAT_REG       GPATOGGLE;    // GPIO Data Toggle Register (GPIO0 to 31)
       union  GPBPUD_REG       GPBDAT;       // GPIO Data Register (GPIO32 to 63)
       union  GPBDAT_REG       GPBSET;       // GPIO Data Set Register (GPIO32 to 63)
       union  GPBDAT_REG       GPBCLEAR;     // GPIO Data Clear Register (GPIO32 to 63)
       union  GPBDAT_REG       GPBTOGGLE;    // GPIO Data Toggle Register (GPIO32 to 63)
       Uint16                  rsvd1[16];

    struct GPIO_INT_REGS {
       union  GPIOXINT_REG     GPIOXINT1SEL; // XINT1 GPIO Input Selection
       union  GPIOXINT_REG     GPIOXINT2SEL; // XINT2 GPIO Input Selection
       union  GPIOXINT_REG     GPIOXNMISEL;  // XNMI_XINT13 GPIO Input Selection
       Uint16                  rsvd2[5];
       union  GPADAT_REG       GPIOLPMSEL;   // Low power modes GP I/O input select

    struct XCLK_BITS   {    // bits  description
       Uint16 XCLKOUTDIV:2; // 1:0   XCLKOUT Divide Ratio
       Uint16 XCLKOUTDAT:1; // 2     reserved for TI use only
       Uint16 X1DAT:1;      // 3     reserved for TI use only
       Uint16 XCLKINDAT:1;  // 4     reserved for TI use only
       Uint16 rsvd1:3;      // 7:5   reserved
       Uint16 X1CNT:4;      // 11:8  reserved for TI use only
       Uint16 XCLKINCNT:4;  // 15:12 reserved for TI use only

    union XCLK_REG {
       Uint16              all;
       struct XCLK_BITS    bit;

    struct PLLSTS_BITS   {    // bits  description
       Uint16 PLLLOCKS:1;     // 0     PLL lock status
       Uint16 CLKINDIV:1;     // 1     CLKIN div by 2
       Uint16 PLLOFF:1;       // 2     PLL off bit
       Uint16 MCLKSTS:1;      // 3     Missing clock status bit
       Uint16 MCLKCLR:1;      // 4     Missing clock clear bit
       Uint16 OSCOFF:1;       // 5     Oscillator clock off
       Uint16 MCLKOFF:1;      // 6     Missing clock detect
       Uint16 rsvd2:9;        // 15:7  reserved

    union PLLSTS_REG {
       Uint16              all;
       struct PLLSTS_BITS  bit;

    struct HISPCP_BITS  {   // bits  description
       Uint16 HSPCLK:3;     // 2:0   Rate relative to SYSCLKOUT
       Uint16 rsvd1:13;     // 15:3  reserved

    union HISPCP_REG {
       Uint16              all;
       struct HISPCP_BITS  bit;

    struct LOSPCP_BITS  {   // bits  description
       Uint16 LSPCLK:3;     // 2:0   Rate relative to SYSCLKOUT
       Uint16 rsvd1:13;     // 15:3  reserved

    union LOSPCP_REG {
       Uint16              all;
       struct LOSPCP_BITS  bit;

    struct PCLKCR0_BITS  {  // bits  description
       Uint16 rsvd1:2;      // 1:0   reserved
       Uint16 TBCLKSYNC:1;  // 2     EWPM Module TBCLK enable/sync
       Uint16 ADCENCLK:1;   // 3     Enable high speed clk to ADC
       Uint16 I2CAENCLK:1;  // 4     Enable SYSCLKOUT to I2C-A
       Uint16 rsvd2:1;      // 5     reserved
       Uint16 SPICENCLK:1;  // 6     Enable low speed clk to SPI-C
       Uint16 SPIDENCLK:1;  // 7     Enable low speed clk to SPI-D
       Uint16 SPIAENCLK:1;  // 8     Enable low speed clk to SPI-A
       Uint16 SPIBENCLK:1;  // 9     Enable low speed clk to SPI-B
       Uint16 SCIAENCLK:1;  // 10    Enable low speed clk to SCI-A
       Uint16 SCIBENCLK:1;  // 11    Enable low speed clk to SCI-B
       Uint16 rsvd3:2;      // 13:12 reserved
       Uint16 ECANAENCLK:1; // 14    Enable system clk to eCAN-A
       Uint16 ECANBENCLK:1; // 15    Enable system clk to eCAN-B

    union PCLKCR0_REG {
       Uint16              all;
       struct PCLKCR0_BITS bit;

    struct PCLKCR1_BITS  {    // bits  description
       Uint16 EPWM1ENCLK:1;   // 0     Enable SYSCLKOUT to EPWM1
       Uint16 EPWM2ENCLK:1;   // 1     Enable SYSCLKOUT to EPWM2
       Uint16 EPWM3ENCLK:1;   // 2     Enable SYSCLKOUT to EPWM3
       Uint16 EPWM4ENCLK:1;   // 3     Enable SYSCLKOUT to EPWM4
       Uint16 EPWM5ENCLK:1;   // 4     Enable SYSCLKOUT to EPWM5
       Uint16 EPWM6ENCLK:1;   // 5     Enable SYSCLKOUT to EPWM6
       Uint16 rsvd1:2;        // 7:6   reserved
       Uint16 ECAP1ENCLK:1;   // 8     Enable SYSCLKOUT to ECAP1
       Uint16 ECAP2ENCLK:1;   // 9     Enable SYSCLKOUT to ECAP2
       Uint16 ECAP3ENCLK:1;   // 10    Enable SYSCLKOUT to ECAP3
       Uint16 ECAP4ENCLK:1;   // 11    Enable SYSCLKOUT to ECAP4
       Uint16 rsvd2:2;        // 13:12 reserved
       Uint16 EQEP1ENCLK:1;   // 11    Enable SYSCLKOUT to EQEP1
       Uint16 EQEP2ENCLK:1;   // 11    Enable SYSCLKOUT to EQEP2

    union PCLKCR1_REG {
       Uint16              all;
       struct PCLKCR1_BITS bit;

    struct PLLCR_BITS {      // bits  description
       Uint16 DIV:4;         // 3:0   Set clock ratio for the PLL
       Uint16 rsvd1:12;      // 15:4  reserved

    union PLLCR_REG {
       Uint16             all;
       struct PLLCR_BITS  bit;

    struct LPMCR0_BITS {     // bits  description
       Uint16 LPM:2;         // 1:0   Set the low power mode
       Uint16 QUALSTDBY:6;   // 7:2   Qualification
       Uint16 rsvd1:7;       // 14:8  reserved
       Uint16 WDINTE:1;      // 15    Enables WD to wake the device from STANDBY

    union LPMCR0_REG {
       Uint16              all;
       struct LPMCR0_BITS  bit;

    struct SYS_CTRL_REGS {
       union   XCLK_REG    XCLK;      // 0
       union   PLLSTS_REG  PLLSTS;    // 1
       Uint16              rsvd1[8];  // 2-9
       union   HISPCP_REG  HISPCP;    // 10: High-speed peripheral clock pre-scaler
       union   LOSPCP_REG  LOSPCP;    // 11: Low-speed peripheral clock pre-scaler
       union   PCLKCR0_REG PCLKCR0;   // 12: Peripheral clock control register
       union   PCLKCR1_REG PCLKCR1;   // 13: Peripheral clock control register
       union   LPMCR0_REG  LPMCR0;    // 14: Low-power mode control register 0
       Uint16              rsvd2;     // 15: reserved
       Uint16              rsvd3;     // 16: reserved
       union   PLLCR_REG   PLLCR;     // 17: PLL control register
       Uint16              SCSR;      // 18: System control and status register
       Uint16              WDCNTR;    // 19: WD counter register
       Uint16              rsvd4;     // 20
       Uint16              WDKEY;     // 21: WD reset key register
       Uint16              rsvd5[3];  // 22-24
       Uint16              WDCR;      // 25: WD timer control register
       Uint16              rsvd6[6];  // 26-31

    volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
    volatile struct GPIO_DATA_REGS GpioDataRegs;
    volatile struct SYS_CTRL_REGS  SysCtrlRegs;

    #define  DINT   asm(" setc INTM")
    #define  EALLOW asm(" EALLOW")
    #define  EDIS   asm(" EDIS")

    cregister volatile unsigned int IFR;
    cregister volatile unsigned int IER;


  • Peter,

    For item #1, please see the workshop manual that Hareesh mentioned earlier in this thread. The workshop uses a local copy of the header files which provides portability and also makes the workshop files self-contained and independent of other support files or resources. However, you could use the default location for the header files by specifying the direct paths in the build options. It might be easier to follow what is done in the workshop.

    To understand the file structure used in the workshop (which can be used for your projects, as well) first see the slide on page 2-18 (page 42). This slide will give you an idea of how the folders are used. You will notice there is an identical copy of the header files, which consists of the three folders - cmd, include, source. Next we have a Lab_common folder with an include folder. Please download the lab code and examine the files in the folders. Note, these files are for the F2837xD, but creating this type of file structure for the F2808 will be very similar.

    Next, review module 3 starting on page 3-1 (page 49). There are three steps required to use the header files - you need to (1) add [#include “F28xx_device.h”] to each source file, (2) add [F2837xD_GlobalVariableDefs.c] to the CCS project, and (3) add a linker command file [F28xx_nonBIOS.cmd] to the CCS project.

    Now see Lab 5 exercise, step 3 on page 5-24 (page 110) for setting up the build options. If you are using the default installation for the header files, change the path to the proper location. Note that the Lab.h file for the workshop is the equivalent to the F28xx_examples.h file in the header files.

    I hope this helps you with getting started with the header files without the need to make any modifications to them.

    - Ken