CCS: XDS560 CCS4 Slow Load Program and Single Step

Hi Rafael,

Thanks much for the quick reply!   I realize this is all old stuff.  

The long cable from the XDS560 to the target board may be showing signs of age - especially if, in your experiments, you simply swapped the PCI card and not the cable.

Interesting, but I'm pretty sure the cables were also swapped without any speed change

Perhaps consider using an older host with Windows XP? If I recall correctly, CCSv4 was never fully tested on Windows 7, therefore giving chance for corner issues to happen. 

I believe both systems (fast and slow) were W7 32-bits or later.  Another question I have is whether I can use anything newer than CCS4 with an XDS560 PCI emulator with a C6722B target?

Also, CCSv4 should still have the xdsprobe utility under ccs_base/common/uscif. You can follow the documentation below to try and dig further and debug its functionality.

Great idea.  I tried the -k test and got the results below.  It says 269905Hz which I assume shows why it is so slow.

C:\Program Files\Texas Instruments\ccsv4\common\uscif>xdsprobe -r -d xds560 -p 0
-k

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 none - 01 00 500.0kHz - differ isit external clock
2 512 -- -- 1.000MHz O good value measure path length
3 512 -- -- 1.000MHz [O] good value test external clock

In the first internal/external clock test:
The expect frequency was 500000Hz.
The actual frequency was 269905Hz.
The delta frequency was 230095Hz.

In the second internal/external clock test:
The expect frequency was 0Hz.
The actual frequency was 0Hz.
The delta frequency was 0Hz.

In the scan-path tests:
The test length was 16384 bits.
The JTAG IR length was 54 bits.
The JTAG DR length was 2 bits.

The IR/DR scan-path tests used 3 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 1.000MHz as the highest frequency.
The IR/DR scan-path tests used 1.000MHz as the final frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

The frequency of the JTAG TCLKR input is measured as 268.7kHz.

The frequency of the JTAG TCLKR input and TCLKO output signals are different.
The target system likely returns a fixed or adaptive TCLKR to the emulator.

C:\Program Files\Texas Instruments\ccsv4\common\uscif>

I find that changing the XDS560 frequency options (and others) seems to have no effect on the speed or functionality whatsoever.  Do you know how that is supposed to work?   Maybe the higher speeds fail and it backs down to the low speed?  Do you know what a compatible Board Data File would be?

Thanks

TK

TK,

Thanks for the additional details. 

Tom Kerekes said:

I believe both systems (fast and slow) were W7 32-bits or later.  Another question I have is whether I can use anything newer than CCS4 with an XDS560 PCI emulator with a C6722B target?

The XDS560 PCI certainly has its support files included in current releases of CCS, as well as C6727 devices. Its Windows drivers are typically located in the directory below:

<CCS_INSTALL_DIR>\ccsv8\ccs_base\emulation\windows\xds560_drivers

Note that this Debug Probe is not supported in 64-bit OSes and I am not sure how the validation and testing are being done nowadays. Unfortunately the number of customers using this Debug Probe is small and there is a chance that bugs may slip under the radar. 

Tom Kerekes said:

I find that changing the XDS560 frequency options (and others) seems to have no effect on the speed or functionality whatsoever.  Do you know how that is supposed to work?   Maybe the higher speeds fail and it backs down to the low speed?  Do you know what a compatible Board Data File would be?

The XDS560 performs a series of tests to evaluate the viability of the connection in face of a TCLK speed - therefore, the number you are getting of ~250kHz is what the channel is able to propagate reliably. However, there is always a chance that a misconfigured target configuration is causing the probe to slow down. 

In the options above, the JTAG TCLK Frequency (MHz) option is set to "automatic", which will make the probe evaluate the best frequency up to the limit. You can try to set it up to Fixed with user specified value and try the various frequencies.

One additional option that may be a limited by the C6727 device is the ability to support the TMS Rising Edge. I would change the option TMS/TDO Output Timing to Falling edge is JTAG standard and retry, 

Actually, I just noticed one thing: your configuration is set to use a 20-pin Rev-D cable, which is rather uncommon. Are you sure you are using a cable like this? 

https://www.blackhawk-dsp.com/store/12198.html 

One short video that could help you is the one below: 

https://youtu.be/mKxaztkCsYw 

Hope this helps,

Rafael

Hi Rafael,

I tried CCS8 which has the same slow speed as CCS4.  The Windows Driver seems to be exactly the same.  CCS8 has the Test button.  Testing many settings never seem to have an effect on the speed and it always reports ~250KHz.

For example these settings:

Gives the report below.  And still runs slow.  

[Start: Texas Instruments XDS560 Debug Probe, 20-pin Rev-D Cable_0]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\TK\AppData\Local\TEXASI~1\CCS\ti\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560/2xx-class product.
This utility will load the program 'xds560.out'.
The library build date was 'Apr 30 2019'.
The library build time was '11:34:49'.
The library package version is '8.1.0.00012'.
The library component version is '35.35.0.0'.
The controller does use a programmable FPGA.
The old VHDL code has a version number of '386336272' (0x17070610).
The new VHDL code has a version number of '386336272' (0x17070610).
The controller has a version number of '6' (0x00000006).
The controller has an insertion length of '0' (0x00000000).
The cable+pod has a version number of '2' (0x00000002).
The cable+pod has a capability number of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the Nano-TBC VHDL.
The link is a 560-class version-B fixed-use old-PLL cable.
The software is configured for Nano-TBC VHDL features.
The controller will be software reset via its registers.
The controller has a logic ONE on its EMU[0] input pin.
The controller has a logic ONE on its EMU[1] input pin.
The controller will use rising-edge timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '3' (0x0003).
The utility logic has not previously detected a power-loss.
The utility logic is not currently detecting a power-loss.

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

  Test  Size   Coord      MHz    Flag  Result       Description
  ~~~~  ~~~~  ~~~~~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
    1   none  - 01 00  500.0kHz   -    differ       isit external clock
    2     64    -- --  --------   O    good value   measure path length
    3     64    -- --  --------  [O]   good value   test external clock

The first internal/external clock test resuts are:
The expect frequency was 500000Hz.
The actual frequency was 274819Hz.
The delta frequency was 225181Hz.

The second internal/external clock test was not done.

In the scan-path tests:
The test length was 2048 bits.
The JTAG IR length was 54 bits.
The JTAG DR length was 2 bits.

The IR/DR scan-path tests used 1 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 500.0kHz as the highest frequency.
The IR/DR scan-path tests used 500.0kHz as the final frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

The frequency of the JTAG TCLKR input is measured as 268.1kHz.

The frequency of the JTAG TCLKR input and TCLKO output signals are different.
The target system likely returns a fixed or adaptive TCLKR to the emulator.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 64 32-bit words.

The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 54 bits.

The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 2 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG IR Integrity scan-test has succeeded.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 64 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.

The JTAG DR Integrity scan-test has succeeded.

[End: Texas Instruments XDS560 Debug Probe, 20-pin Rev-D Cable_0]

Yes I have the 20pin cable and 20pin connector on the back of the XDS560

CCS8 keeps wanting to Update the Emulator and Blackhawk software - which I was hoping would help - but always fail with the below message:

Some sites could not be found. See the error log for more detail.
Unable to read repository at downloads.ti.com/.../content.jar.
Read timed out
Unable to read repository at software-dl.ti.com/.../content.xml.xz.
Read timed out

Updating Software has encountered a problem
An error occurred while collecting items to be installed
session context was:(profile=epp.package.cpp, phase=org.eclipse.equinox.internal.p2.engine.phases.Collect, operand=, action=).
Unable to read repository at downloads.ti.com/.../com.ti.emulation.pack.win32_root.win32.win32.x86_8.3.0.00003.
Read timed out

If you have any other ideas please let me know, otherwise we will just use it slow.

Regards

TK

TK,

The issues with updates shouldn't matter in this regard. I suspect that something specific to this host (or perhaps newer instances of the Operating System) may be getting in the way of a reasonable speed. 

Given the Debug Probe performs signal integrity tests before connecting, there is little that can be done in addition to what was already tried above. Sorry.

Regards,

Rafael