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CCS/MSP430F2417: Reset error using dual image in RAM and ROM

Parama Sivan
Prodigy 60 points
Part Number: MSP430F2417

Tool/software: Code Composer Studio

Hi,

I have used ram memory for bootloader image and flash memory for application firmware. The application firmware creates a copy of the flash image into an external EEPROM and switches into bootloader firmware.

Then the bootloader firmware copies the image from EEPROM to internal flash and runs the application. I am getting a 0xffe reset vector error while jumping into the application from bootloader firmware.

Even I couldn't overwrite the reset vector address of the application from the bootloader.Bootloader reset vector address 0x110A

Application Reset vector address 0xFFFE (default).

I have attached both liker files. Kindly help me with how to handle the reset vector using the dual images in RAM and ROM.

SECTIONS
{
.bss : {} > RAM /* Global & static vars */
.data : {} > RAM /* Global & static vars */
.TI.noinit : {} > RAM /* For #pragma noinit */
.sysmem : {} > RAM /* Dynamic memory allocation area */
.stack : {} > RAM (HIGH) /* Software system stack */

#ifndef __LARGE_CODE_MODEL__
.text : {} > RAM /* Code */
#else
.text : {} >> RAM /* Code */
#endif
.text:_isr : {} > RAM /* ISR Code space */
.cinit : {} > RAM /* Initialization tables */
#ifndef __LARGE_DATA_MODEL__
.const : {} > RAM /* Constant data */
#else
.const : {} >> RAM /* Constant data */
#endif
//.bslsignature : {} > BSLSIGNATURE /* BSL Signature */
.cio : {} > RAM /* C I/O Buffer */

.pinit : {} > RAM /* C++ Constructor tables */
.binit : {} > RAM /* Boot-time Initialization tables */
.init_array : {} > RAM /* C++ Constructor tables */
.mspabi.exidx : {} > RAM /* C++ Constructor tables */
.mspabi.extab : {} > RAM /* C++ Constructor tables */
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#ifndef __LARGE_CODE_MODEL__
.TI.ramfunc : {} load=RAM, run=RAM, table(BINIT)
#else
.TI.ramfunc : {} load=RAM | FLASH2, run=RAM, table(BINIT)
#endif
#endif
#endif

.infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */
.infoB : {} > INFOB
.infoC : {} > INFOC
.infoD : {} > INFOD

/* MSP430 Interrupt vectors */

.reset : {} > RESET /* MSP430 Reset vector */
}

/**************************   Application Linker

MEMORY
{
SFR : origin = 0x0000, length = 0x0010
PERIPHERALS_8BIT : origin = 0x0010, length = 0x00F0
PERIPHERALS_16BIT : origin = 0x0100, length = 0x0100
RAM : origin = 0x2100, length = 0x1000 //modified
INFOA : origin = 0x10C0, length = 0x0040
INFOB : origin = 0x1080, length = 0x0040
INFOC : origin = 0x1040, length = 0x0040
INFOD : origin = 0x1000, length = 0x0040
FLASH : origin = 0x3100, length = 0xCEBE
FLASH2 : origin = 0x10000,length = 0xA000
BSLSIGNATURE : origin = 0xFFBE, length = 0x0002, fill = 0xFFFF
INT00 : origin = 0xFFC0, length = 0x0002
INT01 : origin = 0xFFC2, length = 0x0002
INT02 : origin = 0xFFC4, length = 0x0002
INT03 : origin = 0xFFC6, length = 0x0002
INT04 : origin = 0xFFC8, length = 0x0002
INT05 : origin = 0xFFCA, length = 0x0002
INT06 : origin = 0xFFCC, length = 0x0002
INT07 : origin = 0xFFCE, length = 0x0002
INT08 : origin = 0xFFD0, length = 0x0002
INT09 : origin = 0xFFD2, length = 0x0002
INT10 : origin = 0xFFD4, length = 0x0002
INT11 : origin = 0xFFD6, length = 0x0002
INT12 : origin = 0xFFD8, length = 0x0002
INT13 : origin = 0xFFDA, length = 0x0002
INT14 : origin = 0xFFDC, length = 0x0002
INT15 : origin = 0xFFDE, length = 0x0002
INT16 : origin = 0xFFE0, length = 0x0002
INT17 : origin = 0xFFE2, length = 0x0002
INT18 : origin = 0xFFE4, length = 0x0002
INT19 : origin = 0xFFE6, length = 0x0002
INT20 : origin = 0xFFE8, length = 0x0002
INT21 : origin = 0xFFEA, length = 0x0002
INT22 : origin = 0xFFEC, length = 0x0002
INT23 : origin = 0xFFEE, length = 0x0002
INT24 : origin = 0xFFF0, length = 0x0002
INT25 : origin = 0xFFF2, length = 0x0002
INT26 : origin = 0xFFF4, length = 0x0002
INT27 : origin = 0xFFF6, length = 0x0002
INT28 : origin = 0xFFF8, length = 0x0002
INT29 : origin = 0xFFFA, length = 0x0002
INT30 : origin = 0xFFFC, length = 0x0002
RESET : origin = 0xFFFE, length = 0x0002
}

/****************************************************************************/
/* Specify the sections allocation into memory */
/****************************************************************************/

SECTIONS
{
.bss : {} > RAM /* Global & static vars */
.data : {} > RAM /* Global & static vars */
.TI.noinit : {} > RAM /* For #pragma noinit */
.sysmem : {} > RAM /* Dynamic memory allocation area */
.stack : {} > RAM (HIGH) /* Software system stack */

#ifndef __LARGE_CODE_MODEL__
.text : {} > FLASH /* Code */
#else
.text : {} >> FLASH2 | FLASH /* Code */
#endif
.text:_isr : {} > FLASH /* ISR Code space */
.cinit : {} > FLASH /* Initialization tables */
#ifndef __LARGE_DATA_MODEL__
.const : {} > FLASH /* Constant data */
#else
.const : {} >> FLASH | FLASH2 /* Constant data */
#endif
.bslsignature : {} > BSLSIGNATURE /* BSL Signature */
.cio : {} > RAM /* C I/O Buffer */

.pinit : {} > FLASH /* C++ Constructor tables */
.binit : {} > FLASH /* Boot-time Initialization tables */
.init_array : {} > FLASH /* C++ Constructor tables */
.mspabi.exidx : {} > FLASH /* C++ Constructor tables */
.mspabi.extab : {} > FLASH /* C++ Constructor tables */
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#ifndef __LARGE_CODE_MODEL__
.TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT)
#else
.TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT)
#endif
#endif
#endif

.infoA : {} > INFOA /* MSP430 INFO FLASH Memory segments */
.infoB : {} > INFOB
.infoC : {} > INFOC
.infoD : {} > INFOD

/* MSP430 Interrupt vectors */
RESERVED0 : { * ( .int00 ) } > INT00 type = VECT_INIT
RESERVED1 : { * ( .int01 ) } > INT01 type = VECT_INIT
RESERVED2 : { * ( .int02 ) } > INT02 type = VECT_INIT
RESERVED3 : { * ( .int03 ) } > INT03 type = VECT_INIT
RESERVED4 : { * ( .int04 ) } > INT04 type = VECT_INIT
RESERVED5 : { * ( .int05 ) } > INT05 type = VECT_INIT
RESERVED6 : { * ( .int06 ) } > INT06 type = VECT_INIT
RESERVED7 : { * ( .int07 ) } > INT07 type = VECT_INIT
RESERVED8 : { * ( .int08 ) } > INT08 type = VECT_INIT
RESERVED9 : { * ( .int09 ) } > INT09 type = VECT_INIT
RESERVED10 : { * ( .int10 ) } > INT10 type = VECT_INIT
RESERVED11 : { * ( .int11 ) } > INT11 type = VECT_INIT
RESERVED12 : { * ( .int12 ) } > INT12 type = VECT_INIT
RESERVED13 : { * ( .int13 ) } > INT13 type = VECT_INIT
RESERVED14 : { * ( .int14 ) } > INT14 type = VECT_INIT
RESERVED15 : { * ( .int15 ) } > INT15 type = VECT_INIT
USCIAB1TX : { * ( .int16 ) } > INT16 type = VECT_INIT
USCIAB1RX : { * ( .int17 ) } > INT17 type = VECT_INIT
PORT1 : { * ( .int18 ) } > INT18 type = VECT_INIT
PORT2 : { * ( .int19 ) } > INT19 type = VECT_INIT
RESERVED20 : { * ( .int20 ) } > INT20 type = VECT_INIT
ADC12 : { * ( .int21 ) } > INT21 type = VECT_INIT
USCIAB0TX : { * ( .int22 ) } > INT22 type = VECT_INIT
USCIAB0RX : { * ( .int23 ) } > INT23 type = VECT_INIT
TIMERA1 : { * ( .int24 ) } > INT24 type = VECT_INIT
TIMERA0 : { * ( .int25 ) } > INT25 type = VECT_INIT
WDT : { * ( .int26 ) } > INT26 type = VECT_INIT
COMPARATORA : { * ( .int27 ) } > INT27 type = VECT_INIT
TIMERB1 : { * ( .int28 ) } > INT28 type = VECT_INIT
TIMERB0 : { * ( .int29 ) } > INT29 type = VECT_INIT
NMI : { * ( .int30 ) } > INT30 type = VECT_INIT
.reset : {} > RESET /* MSP430 Reset vector */
}

/****************************************************************************/
/* Include peripherals memory map */
/****************************************************************************/

-l msp430f2417.cmd

Thanks,

Param.

  • 0
    TI__Mastermind 32900 points

    Hi,

    1. From where you download the BSL code into RAM? You directly download it using CCS?

    2. Why it has a relationship with ROM? What do you put in ROM?

    3. What the problem when you  "handle the reset vector using the dual images in RAM and ROM"?

    Eason

  • 0
    TI__Mastermind 32900 points

    Hi,

    Have you made any progress?

    Eason

  • 0 in reply to Eason Zhou
    Prodigy 60 points

    Hi Eason,

    Sorry for the late replay due to holidays.

    Yes, it is working once I changed the bootloader reset address into 0xFFE0.

    Bootloader source code in RAM from 0x1100. After changing my reset address, I couldn't debug through the compiler since no value in the default reset address(0xfffe).

    From the application firmware, I have copied the application firmware into external EEPROM also copied the vector table up to the reset vector address.  Once Copied, I jump into bootloader main and copy the firmware from EEPROM into internal flash memory with vector table (BSLSIGNATURE: origin = 0xFFBE  to RESET: origin = 0xFFFE).

    At the end of the copy function (in Bootloader), I just called the  WDTCTL = 0x00 to reset to RUN the new application firmware. 

    It Works now :)

    Note:

    I noticed after erase the flash memory if I skip the BSLSIGNATURE value (as 0xffff) in the vector table write, it didn't work.

    Thanks,

    Param.

  • 0 in reply to Parama Sivan
    Prodigy 60 points

    Reset Vector address of bootloader is 0xFF00.

  • 0 in reply to Parama Sivan
    TI__Mastermind 32900 points

    Hi Param,

    It is nice to hear that you solve it by yourself.

    As you say"Bootloader source code in RAM from 0x1100. After changing my reset address, I couldn't debug through the compiler since no value in the default reset address(0xfffe).", you can put the bootloader entrance address into PC in debug mode, then you can debug it.

    Eason 

  • 0 in reply to Eason Zhou
    Prodigy 60 points

    Oh Really !!! ???

    How to do that?? Sorry, I am new to CCS. Thanks for your help.

    Thanks.

  • 0 in reply to Parama Sivan
    TI__Mastermind 32900 points

    Hi

    It is OK. I am not at office, so I can't show you directly. Please see the picture bellow, in Registers views, find CPU registers, then find PC, double cilck its value, then input the address, then press "enter", then it works.

    Eason