Code Composer Studio forum - Recent Threads

TMDSEMU200-U: XDS200: Windows ARM64 Driver Support for Snapdragon-Based Laptops

Sang-il Nam — Thu, 12 Nov 2026 00:15:36 GMT

Part Number: TMDSEMU200-U
Other Parts Discussed in Thread: CCSTUDIO

Hello TI team,

A customer is using a Snapdragon-based laptop running Windows on Arm (ARM64) and is having difficulty getting an XDS200-class debug probe recognized over USB.

I found the following related E2E discussion:

TMS320F28377D: xds200 arm64 based on windows driver

The TI response indicated that CCS did not officially support Windows on Arm at that time and that potential future support would likely focus on XDS110.

Could you please clarify the current status with CCStudio v21.0.1 and the latest TI Emulation Software Package?

Current Windows ARM64 support: Is a signed, ARM64-compatible USB driver package available for XDS200? Is this configuration officially supported or known to work?
Kernel driver versus installation package: XDS200 normally appears in Device Manager as an “XDS2xx Emulator CDC Serial Port.” Does it require a TI-specific kernel-mode driver, or can it use the built-in Windows ARM64 USB CDC/serial driver with an appropriate INF package? We would like to understand whether the limitation is in the kernel driver, the INF/installer package, or another component of the CCS debug stack.
Available workaround: Is there any TI-recommended or tested procedure that allows an existing XDS200 probe to work directly over USB with a Snapdragon-based Windows laptop?
Support roadmap: If this configuration is currently unsupported, are there plans to support XDS200 specifically on Windows ARM64? If so, is there an estimated release timeframe?

Our goal is to continue using the existing XDS200 probe with the customer’s Snapdragon laptop.

Thank you for your guidance.

Best regards,
Sangil, Nam

CODECOMPOSER: Code Composer Studio Resource Explorer does not work

cuong thai — Wed, 11 Nov 2026 13:49:33 GMT

Part Number: CODECOMPOSER
Other Parts Discussed in Thread: TMS320F28388D

Hello,

My microcontroller is TMS320F28388, which has two C28x cores (CPU1, CPU2) and one ARM M4 (CM) cores. I am trying to get the AES encryption/decryption examples for the ARM M4 (CM)

1) I have trouble in getting the example design in Code Composer Studio 12.8.1.00005 Resource Explorer. I have Here is the message when I open Resource Explorer:

"Cannot GET /tirex4-desktop"

Then I went to Resource Explore Offline, I see the Welcome to Resource Explorer, The page is loaded, then the drop down on upper left (Select a Device or Board) shows: "Show All", Development Tools", "Devices", but nothing happens.

The issues above are persistent in multiple computers with both Windows and Linux,

2) I tried Code Composer Studio 20.0.1.00010 and 20.0.0.00012, I can be sample design for C28x from Resource Explorer, but not CM (M4 Arm). Here is the here when I go to

"C2000 real time microcontroller" -> "Embedded Software"->"C2000Ware-26.02.00.00"->"English"->"Devices"->"F28388XD"->"F28388D"->"Example"-> "Devicelib"->"cm"->"aes"-"aes_ex4_gcm_decrypt", then "Import":

"No TI Arm compilers, supporting device 'TMS320F28388D [Cortex M]', are currently installed"

3) I tried TI online Resource Explore webside: https://dev.ti.com/tirex/explore: with same step as 2):

a webpage pops up and shows this message:

"We are currently upgrading our systems.
Please try again later."

Thanks,

Cuong Thai

TMS320F28P650DH: Flash Settings in Project Properties → Debug are saved to the first launch configuration in launch.json, not the selected build configuration

AN eunji — Wed, 11 Nov 2026 08:48:58 GMT

Part Number: TMS320F28P650DH
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

Hello,

I think I’ve found an issue with how CCS 21 saves debugger Flash Settings when a project has more than one build configuration.

CCS version: 21.0.1 (build [build number]), Device: TMS320F28P650DH6
The project has two build configurations, FLASH and DEBUG, and <project>\.theia\launch.json contains two launch configurations: cpu1_FLASH and cpu1_DEBUG.
Steps to reproduce: Project Properties → Debug (with the DEBUG configuration selected) → Flash Settings → change the Bank Map → Save and Close
Expected result: the debuggerSettings of the cpu1_DEBUG block is updated.
Actual result: the first launch configuration in launch.json (cpu1_FLASH) is updated instead. If I change the order of the blocks, the block that gets updated changes with it.

F29H85X-SOM-EVM: F29H85x (C29x): read memory of a running core without halting it, as on C28x

Nehemiae George Roy — Tue, 10 Nov 2026 18:26:55 GMT

Part Number: F29H85X-SOM-EVM

Setup: F29H850TU9, F29H85X-SOM-EVM, XDS110, CCS 20.5.0. The cores run flash images; the debugger connects without halting (Halt the target on a connect: off).

C28x (for example F28379D, F28P65x): we connect to a running core and read variables in the Expressions and Memory views while it keeps running. No halt is needed.

The same script on both (CCS 20.5 scripting; a free-running counter in the application; ccxml with the GEL files removed). Only the core name differs:

const ds = initScripting();
ds.configure("board_noGEL.ccxml");
const session = ds.openSession(/C28xx_CPU1/i);   // F29H85x: /C29xx_CPU1/i
session.settings.set("HaltOnConnect", false);
session.target.connect();
session.symbols.load("dummy_CPU1.out");
console.log(session.target.isHalted());          // false on both: the core keeps running
console.log(session.expressions.evaluate("counterDummyCPU1"));

On C28x the last line returns the value, and a second read shows it advancing. On F29H85x it fails, as does every other memory or register access:

Could not read 0x20120494: execution state prevented access

Enabling real-time mode doesn't help (GEL_EnableRealtime() returns "Realtime must be supported to evaluate"). Reads work only with "Halt the target before any debugger access", which halts the core on every access, or after we halt and run the core once in that debug session.

Questions:

Is there a supported way to read memory of a running C29x core without any halt, like on C28x?
If one halt per debug session is required, is that intended, and is real-time mode planned for C29x?

Background: we monitor running control applications (power stage on), where halting the core isn't acceptable.

SYSCONFIG: pin mux pin name issue

Philippe STROOBANT — Tue, 10 Nov 2026 14:08:21 GMT

Part Number: SYSCONFIG
Other Parts Discussed in Thread: MSPM0C1106

Hello

when i switch from MSPM0C1106 to MSPM0C1106 LAUNCHPAD with the sysconfig IDE, pin designation change from "PAxx" to "0.yy" and build is broken

TMS570LS3137: Required DSS handbook and index debug scripting files for Code composer studio version 10.1.1

Bharadwaj KS — Tue, 10 Nov 2026 09:07:40 GMT

Part Number: TMS570LS3137

our development environment is Code Composer Studio (CCS) v10.1.1.

needed DSS (Debug Server Scripting) support files/documentation for CCS v10.1.1.

1)DSS handbook

2)Index debug scripting files

Attaching the files for your reference, which is for code composer studio version 21.0.1

sdto_dss_handbook.html index_debug-scripting.html

CCSTUDIO-THEIA: CCS Theia v21: Keyboard shortcuts interfere with Japanese IME composition

Tetsuma Hoshino — Tue, 10 Nov 2026 04:57:26 GMT

Part Number: CCSTUDIO-THEIA

I am using CCS Theia v21 on Windows with a Japanese IME.

While composing Japanese text in the editor, pressing Ctrl+P or Ctrl+O triggers CCS keyboard shortcuts instead of allowing the IME to handle these keys.

These key combinations are used for character conversion in Japanese IME keymaps.

**Expected behavior:**

Keyboard shortcuts should not interfere with active IME composition. They should continue to work normally when IME composition is inactive.

**Actual behavior:**

CCS processes these key combinations as IDE shortcuts during IME composition, interrupting Japanese text input.

**Relevant upstream implementation:**

Eclipse Theia has implemented IME-aware keyboard shortcut handling, including checks for KeyboardEvent.isComposing and keyCode === 229.

A related improvement was merged in Eclipse Theia PR #17723:

https://github.com/eclipse-theia/theia/pull/17723

Please investigate and correct the keyboard shortcut handling during IME composition in CCS Theia.

Sincerely,

F29H85X-SOM-EVM: [SysCfg] How to change Default sections included in Link2?

ky pham — Mon, 09 Nov 2026 11:17:53 GMT

Part Number: F29H85X-SOM-EVM
Other Parts Discussed in Thread: SYSCONFIG

Hi Team,

I am currently facing an issue when using the SysConfig Tool in CCS.

My software does not use board.c, ssu_config.c, or device.c, and I have already excluded these files in the Generate Files option. However, when I check the default sections included in Link2, device.o, board.o, and ssu_config.o are still added to the generated linker configuration.

As a result, the software build fails every time I trigger Build Project in CCS.

Do you have any suggestions on how to remove these object files from the generated linker configuration or resolve this issue?

Thank you in advance.

CCSTUDIO-THEIA: Theia or Vs Code

Hakan B — Mon, 09 Nov 2026 11:10:30 GMT

Part Number: CCSTUDIO-THEIA
Other Parts Discussed in Thread: CCSTUDIO, SYSCONFIG

Hello,

I have been using CCS since version 5 or 6. I didnt switch to theia (v20+) and still using CCS v12.8.x.

CCS-theia is similar to VS code. Last week, I saw on TI's youtube page that you have added CCS plugins to VS code. HERE: https://www.youtube.com/watch?v=RCdatQTU2P8

What is your roadmap for IDE? Shall we use theia or vs code with CCS plugin for future development? What will be their difference? I am confused.

Regards,
Hakan

TPS65994AE: TYPE-C no display

Michael Lin — Mon, 09 Nov 2026 05:13:11 GMT

Part Number: TPS65994AE

Hi , Sean :

I try to measurement some signal when the type-c monitor plug-in ~~

It looks like not normal ……..

Why the CC is +5V ? And when plug-in , it oscillation and down to ~+2V
The SBU only ~200mV ?
The HPD signal is no detect ?

Could you help to check and replay ASAP ?

LP-EM-CC2745R10-Q1: debug authentication mode

Obinna Ezeilo — Thu, 05 Nov 2026 17:51:54 GMT

Part Number: LP-EM-CC2745R10-Q1
Other Parts Discussed in Thread: AWRL1432BOOST-BSD,

Hi Team,

My customer is trying to use the AWRL1432BOOST-BSD and LP-EM-CC2745R10-Q1 to prototype a demo from Radar Toolbox (www.ti.com/.../6356159234112). Question:

Does the LP-EM-CC2745R10-Q1 ship with debug authentication off in its default CCFG?

Kind regards,

CODECOMPOSER: AI Solution Review Questionnaire for Code Composer Studio AI Features

xu pinjin — Thu, 05 Nov 2026 07:50:54 GMT

Part Number: CODECOMPOSER

Hello TI Team,

We are evaluating the AI capabilities available in Code Composer Studio (CCS 12.2) and would appreciate your support in answering the following questions regarding AI functionality, data handling, security, compliance, and deployment.

1. What value does the AI add to CCS and what are the primary use cases?

2. Which data are used by the AI service?

3. Please confirm whether customer data, source code, prompts, or uploaded content are used for AI model training.

4. How do you ensure that customer data is not used for AI model training?

5. Is the AI hosted by TI or by an external provider? If external, which provider is used?

6. Do TI contractual terms also apply to the AI provider and its services?

7. How are data retention, storage location, encryption, and data processing managed?

8. Is customer data processed and stored in Europe?

9. Is the solution compliant with GDPR and the EU AI Act? If applicable, please provide information regarding AI risk classification and associated documentation.

10. What protections exist against data poisoning, prompt injection, unauthorized disclosure, or unintended use of customer data?

11. What monitoring, logging, and auditing capabilities are available for administrators?

12. How is AI usage licensed and billed? If token-based consumption is used, are there mechanisms for quota limits, spending caps, blocking, or usage control?

13. Can sensitive information be filtered, masked, or excluded before being sent to the AI service?

14. Can the AI be used for purposes other than its original intended use case?

15. Can customers customize AI guardrails, restrictions, or usage policies?

16. Can the AI be used as part of an agentic workflow, orchestration framework, or automation process initiated by another application or AI system?

17. Are AI responses generated based on the user's permissions and access rights?

18. Can AI functionality be completely disabled by administrators or customers?

19. Does the AI connect to or rely on any MCP (Model Context Protocol) servers? If yes, are these servers operated by TI or third-party providers?

20. Does CCS allow customers to integrate their own AI provider or LLM service instead of the default AI backend?

Additional information:

- Product: Code Composer Studio (CODECOMPOSER)

- Version: CCS 12.2

- Purpose: Internal evaluation of AI security, compliance, governance, and technical capabilities.

Thank you for your support.

CCSTUDIO-THEIA: Garbled characters in the build log

Takayuki Kato — Wed, 04 Nov 2026 08:21:31 GMT

Part Number: CCSTUDIO-THEIA

I am using CCS Version: 21.0.1.10__1.12.1 (Windows/Japanese version).
When I run the build, the log display shows garbled characters.
(After running Clean Projects, run Build Projects, Clean Projects, etc.)

Changing the "UTF-8" setting at the bottom right makes no difference (The text remains garbled).

Best regards,
Kato T.

CCSTUDIO-THEIA: How to create a project

Takayuki Kato — Wed, 04 Nov 2026 02:47:36 GMT

Part Number: CCSTUDIO-THEIA

I am currently using CCS Version: 21.0.1.10__1.12.1 (Windows).
I have the following folder structure:

In such a case, what is the proper way to create a new ProjXX?
Currently, I am working on the following steps:
1. Create ProjXX in the current folder (within CCS).
2. Move ProjXX to the desired location (folder) (using Windows Explorer).

There are two related issues.
1. How can I open ProjA directly?
How can I open ProjA directly from Windows Explorer?
Currently, I've associated CSS with a folder and launch CSS by right-clicking (Shift+) on the folder.
2. What is the proper way to rename a project?
For example, ProjA --> ProjD
Currently, I open the parent folder in CCS and renaming it there.

Best regards,
Kato T.

CCSTUDIO-THEIA: CCSTUDIO-THEIA: How to add include paths

Takayuki Kato — Wed, 04 Nov 2026 02:02:24 GMT

Part Number: CCSTUDIO-THEIA

I am currently using CCS Version: 21.0.1.10__1.12.1.
I am using an external library (WIZnet).
I don't understand how to specify the additional include path for it.
I do know that I need to add it via this screen, though.

For a single source file (e.g, main.c), I can add it by selecting the filename and right-clicking to select [Properties...].
However, I don't know of a reliable way to add this to all source files (*.c).

A related issue is that include specifications do not take effect when the "-Iquote" option is used.
The build log showed the string "-Iquote xxxx", but it was not enabled (specified with double quotes "").
Specifying with "-I" is valid.

Best regrads.

MSPM33C321A: CCS 21.0.1.00010: endless "settings changed, restart required" loop and exception when opening .syscfg of imported MSPM33 examples

Lukas Hablowetz — Tue, 03 Nov 2026 11:02:21 GMT

Part Number: MSPM33C321A
Other Parts Discussed in Thread: SYSCONFIG

Hi,

with CCS V1.04.00.00 on Windows 11 Pro (Version 10.0.26200, 64 bit) I have two problems:

After every start CCS reports that settings have changed and CCS has to be restarted. Clicking "Restart" ends in an endless loop. If I cancel, CCS seems to work.
I imported several MCAN examples from the MSPM33 SDK [V1.04.00.00]. Opening the .syscfg file fails with an exception: [Fehlertext aus Screenshot]. Confirming the dialog with "Yes" again ends in an endless loop.

Deleting the affected projects and importing them again makes the SysConfig editor work, but not permanently. I did not check whether CCS damages the configuration files or whether there is another cause.

Questions:

Is this a known issue in CCS 21.0.1?
Which logs should I provide (workspace .metadata/.log, CCS/Theia logs) to analyze it?

Thanks and kind regards

CCSTUDIO: Several applications on TI Developer Zone (dev.ti.com) are not available due to maintenance

Ki — Mon, 02 Nov 2026 13:29:09 GMT

Part Number: CCSTUDIO
Other Parts Discussed in Thread: UNIFLASH, SYSCONFIG

Several apps on TI Developer Zone (dev.ti.com) are not currently accessible due to maintenance. This currently impacts CCS Cloud, GUI Composer, the online versions of Edge AI Studio, UniFlash, and SysConfig. We apologize for the inconvenience. We are working to restore access as soon as possible.

Resource Explorer and Gallery are available.

TMS320C6678: Previously available compiler for C6000 series is not available anymore

Andreas Antes — Mon, 02 Nov 2026 07:50:54 GMT

Part Number: TMS320C6678
Other Parts Discussed in Thread: C6000-CGT

The previously availabe compiler 8.5.0.LTS seems to be not available anymore.

We rely on downloading the compilers in our build infrastructure to build docker containers and it seems that this compiler is not available anymore.

Neither through a direct link, nor on the official website.

What is the reason for it? Can you please assist?

CCSTUDIO-THEIA: debug console usage and inspecting a variable

David Regan — Fri, 30 Oct 2026 11:08:54 GMT

Part Number: CCSTUDIO-THEIA
Other Parts Discussed in Thread: TMDS64EVM, CCSTUDIO

I've just loaded CCS v21.0 and am debugging an example application on the m core of am64.
I would like to be able to examine a variable e.g. cnt. In vscode and earlier Eclipse systems I can go to the Debug Console and type things like

cnt
&cnt
cnt & 0x3f

This does not seem possible. Anything I enter in the debug console reports Invalid Frame Index. Surely I don't have to add it to the watch window, view it, and then delete it.

I would like the previous behaviour of an immediate window.

Is this possible?

CCSTUDIO-THEIA: CCSTUDIO-THEIA: How can I export raw data from TI (Texas Instruments) as 16-bit values in CCS version 21.0?

Andrew Kong — Fri, 30 Oct 2026 05:51:02 GMT

Part Number: CCSTUDIO-THEIA
Other Parts Discussed in Thread: TMS320F2800137

Fig1 memory data

Fig2 Data without swap

Fig3 Data with swap and 16 bit

Fig4 Data swap 16 bit then disable swap

Fig5 Data in V12.2 with no swap 16 bit

Fig6 export data set in V21.0

Fig7 export data in V12.2

Hi,

I want to get the real memery data from flash.

The chip is tms320f2800137

In CCS Vesion 12.2 , it can export memory data from flash with set "TI RAW DATA NO SWAP 16 bit". See Fig7 & Fig5. It's same with the real memory data ,see Fig1 & Fig5.
In CCS Version21.0, no matter how I set, I can't get the real memory data . See Fig2~Fig6
It seems like can't export "no swap & 16 bit TI RAW DATA" memory data
How to reserver this problem
I have posted threads here before, but it forbidden now

TMS320F28P650DH: CPU2 Error erasing Bank 2 on device that doesn't have a Bank 2

Jason Galtieri1 — Thu, 29 Oct 2026 20:15:13 GMT

Part Number: TMS320F28P650DH

Hello,

When trying to flash CPU2 from code composer I am getting an error

C28xx_CPU2: Flash Programmer: Error erasing Bank 2 FMSTAT (STATCMD on some devices) value = 65. Operation Cancelled (0).
C28xx_CPU2: File Loader: Memory write failed: Unknown error

However, the DH6 does not have a Bank 2 of Flash only 0,1 and 4.

I have the correct device number set in the project properties and the target config, so I don't know where the Bank 2 setting is coming from. Flash settings in debug config only list Banks 0, 1, and 4

Additionally from console output CPU1 is trying to erase Banks 0-3 so there seems to be a settings issue I am unaware of that is messing up intialization values

C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected CPU1/CPU2 flash banks executable are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: Writing Flash @ Address 0x00080000 of Length 0x00000002 (page 0)
C28xx_CPU1: GEL Output: ... DCSM Initialization Start ...
C28xx_CPU1: GEL Output: ... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
CPU2 is out of reset and configured to wait boot.
(If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GSxMSEL register configured correctly
C28xx_CPU1: BankMuxSel register configured correctly
C28xx_CPU1: PLL configuration status = 1. PLL configured successfully.
C28xx_CPU1: Erasing Flash Bank 0
C28xx_CPU1: Erasing Flash Bank 1
C28xx_CPU1: Erasing Flash Bank 2
C28xx_CPU1: Erasing Flash Bank 3
C28xx_CPU1: Data has been buffered at the end of the current data block for 64-bit aligned writes.
C28xx_CPU1: Writing Flash @ Address 0x00080008 of Length 0x00000b09 (page 0)
C28xx_CPU1: Data has been buffered at the end of the current data block for 64-bit aligned writes.
C28xx_CPU1: --Verifying Flash @ Address 0x00080008 of Length 0x00000B08
C28xx_CPU1: Writing Flash @ Address 0x00080b18 of Length 0x0000005b (page 0)
C28xx_CPU1: Data has been buffered at the end of the current data block for 64-bit aligned writes.
C28xx_CPU1: --Verifying Flash @ Address 0x00080B18 of Length 0x00000058
C28xx_CPU1: Writing Flash @ Address 0x00080b78 of Length 0x00000044 (page 0)
C28xx_CPU1: --Verifying Flash @ Address 0x00080B78 of Length 0x00000044
C28xx_CPU1: Writing Flash @ Address 0x00080bc0 of Length 0x00000012 (page 0)
C28xx_CPU1: Data has been buffered at the end of the current data block for 64-bit aligned writes.
C28xx_CPU1: --Verifying Flash @ Address 0x00080BC0 of Length 0x00000010
C28xx_CPU1: Writing buffered data @ Address 0x00080000 of Length 0x00000004
C28xx_CPU1: --Verifying Flash @ Address 0x00080000 of Length 0x00000004
C28xx_CPU1: Writing buffered data @ Address 0x00080B10 of Length 0x00000004
C28xx_CPU1: --Verifying Flash @ Address 0x00080B10 of Length 0x00000004
C28xx_CPU1: Writing buffered data @ Address 0x00080B70 of Length 0x00000004
C28xx_CPU1: --Verifying Flash @ Address 0x00080B70 of Length 0x00000004
C28xx_CPU1: Writing buffered data @ Address 0x00080BD0 of Length 0x00000004
C28xx_CPU1: --Verifying Flash @ Address 0x00080BD0 of Length 0x00000004
C28xx_CPU2: GEL Output:

RAM initialization done

C28xx_CPU2: GEL Output:
Memory Map Initialization Complete
C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after the selected CPU1/CPU2 flash banks executable are programmed.
C28xx_CPU2: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, and CPU2 Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 200MHz using INTOSC as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU2: Before doing any flash operations using the flash plugin, (a) Please select which flash banks should be mapped to which CPU (CPU1 vs CPU2) - This selection should be done in CPU1 flash plugin GUI. (b) Please select the flash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
C28xx_CPU2: Writing Flash @ Address 0x00100000 of Length 0x00000002 (page 0)
C28xx_CPU2: GSxMSEL register configured correctly
C28xx_CPU2: Erasing Flash Bank 2
C28xx_CPU2: Flash Programmer: Error erasing Bank 2 FMSTAT (STATCMD on some devices) value = 65. Operation Cancelled (0).
C28xx_CPU2: File Loader: Memory write failed: Unknown error
C28xx_CPU2: GEL: File: C:

CCSTUDIO-THEIA: How to export raw EnergyTrace current-versus-time data in CCS Theia 1.3.1.4?

Wang Li — Thu, 29 Oct 2026 16:59:05 GMT

Part Number: CCSTUDIO-THEIA
Other Parts Discussed in Thread: ENERGYTRACE, LP-MSPM0G3507

hi,

I'm using Code Composer Studio Theia 1.3.1.4 on Windows with an LP-MSPM0G3507 LaunchPad and EnergyTrace.

I can successfully capture EnergyTrace measurements and view the current plots and raw measurements in the Records table.

However, the only CSV export option I can find is under the Summary view, which exports aggregate statistics rather than the time-resolved measurements.

I also cannot copy the Records table using Ctrl+A/Ctrl+C.

Is there a supported way to export the full time-resolved EnergyTrace data (timestamps, current, and voltage) in CCS Theia 1.3.1.4? If not, is there a command-line tool, trace file, or API that provides access to the underlying capture data?

I'm specifically interested in analyzing transient current consumption during microSD writes.

thanks.

MSPM33-SDK-DESIGN: Need assistance to fix include files

BALAJI SARAVANAKUMAR — Wed, 28 Oct 2026 12:02:12 GMT

Part Number: MSPM33-SDK-DESIGN

Hello team, here I have changed the code using the above conversion from dynamic directiry to direct file include. I am trying to include the header files in the include path of the CCS instead of giving dynamic directory in the code. The problem I am facing is, after including the header files in CCS, still I am getting build error. Few files are included but few are not included. We want to know whether we are correct in including the files.

For one file it is included but for other it is not included

Whether this approach is right or we need to include somewhere else? Please help us fixing the issue.

CCSTUDIO-THEIA: Database file compile_commands.json generation from CCStudio ccs-server-cli

Guido Pagani — Wed, 28 Oct 2026 09:27:33 GMT

Part Number: CCSTUDIO-THEIA
Other Parts Discussed in Thread: CCSTUDIO

Hi,

I would like to have the "compile_commands.json" file generated/updated when building from the command line in CCStudio 21.0.1.10.

I noticed that the ".clangd" folder, which usually contains that file, is generated when building from the IDE GUI via the "Build Projects" menu item.

When compiling the same project using ccs-server-cli.bat the ".clangd" folder is not being generated/updated despite all the other output files are generated inside the configuration build folder. Also the "ccs: project-build output" of the IDE GUI and the cli output are the same.

Any hint on how to generate the compile_commands.json file via ccs-server-cli.bat ?

MSPM33-SDK: How to manage the included files in the project ?

Sebastien Le Diouris — Wed, 28 Oct 2026 08:57:12 GMT

Part Number: MSPM33-SDK

Hello,

in my project, as I have any folders, when I want to include a file in other folder I am obliged to do this:

My question is how to do, to declare the included files like this (without path):

I try to add the different paths here, without success:

Could you tell me how to do, please ?

Thanks