https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/Before making a post please check the <a href="http://processors.wiki.ti.com/index.php/Category:CCS%20">CCS wiki</a> which contains detailed documentation, tutorials and FAQs. en-USTelligent Community 13https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1686782/mspm33-sdk-sizeof-for-structure-and-alignmentFri, 02 Oct 2026 11:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c8c3cfa9-e52c-4208-a77b-fff7a9b629e4Sebastien Le DiourisPart Number: MSPM33-SDK Other Parts Discussed in Thread: MSPM33C321A Hello, I&#39;m working on MSPM33C321A on CCS, I have declared a structure where inside there are other structures, like this: typedef struct { sStructure1 S_struct1; uint16_t u16Data1; sStructure2 S_struct2; sStructure3 S_struct3; sStructure4 S_struct4; sStructure5 S_struct5; sStructure6 S_struct6; sStructure7 S_struct7; uint16_t u16Data2; }MainStructure; I check that: sizeof(MainStructure) is not equal to sizeof (sStructure1) + sizeof(u16Data1) + sizeof (sStructure2) + sizeof (sStructure3) + .... + sizeof (sStructure7) + sizeof(u16Data2) But if the int16_t are moved by uint32_t, I have : sizeof(MainStructure) = sizeof (sStructure1) + sizeof(u32Data1) + sizeof (sStructure2) + sizeof (sStructure3) + .... + sizeof (sStructure7) + sizeof(u32Data2) I checked in linker file, and the alignment are declare on 16 bits Could you tell me if it possible to fix this issue ? ThanksMSPM33C321AMSPM33-SDKhttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1686338/tms570ls1227-segger-j-link-usage-with-cortex-r/6499166Thu, 01 Oct 2026 04:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e5ce1eef-38bd-41c1-b168-41a24f57445ejagadish gundavarapuHi Jacob, I never came across this issue before, on first level could you please verify below of our internal AI suggestions: Issue 1: &quot;Break at Address 0x0&quot; on Connect This is almost always caused by one of the following: Root Cause A: ECC Initialization Conflict The TMS570LS1227 runs a hardware ECC initialization routine in ROM before reaching your code. The J-Link interrupts this and lands at 0x0. Fix - Verify your JLinkScript is actually being loaded: // In CCS Debug Configuration: // Target &gt; J-Link &gt; JLinkScript file field // Confirm the FULL absolute path is specified, not relative // e.g., C:/JLink/Scripts/TI_TMS570Lx_SkipECCInit.JLinkScript Check the J-Link log output in CCS console for: Script: Found and executed If you do NOT see this, the script is silently failing to load. Root Cause B: Reset Handling Misconfiguration In your CCS Debug Configuration, verify these settings under Target &gt; Reset Configuration : Setting Recommended Value Reset Type Core Reset (not System Reset) Reset at connect Disabled initially for live debug Halt after reset Disabled for connect-to-running Issue 2: Endianness Mismatch Error When Using JLinkScript This is the key issue and is likely masking everything else. What&#39;s Actually Happening The TMS570LS1227 is a big-endian Cortex-R4F. The J-Link drivers sometimes misidentify endianness when a JLinkScript modifies the connection sequence. Verify your .ccxml target configuration: JLinkScript Endianness Declaration The provided SEGGER script may be missing or have an incorrect endianness declaration. Open TI_TMS570Lx_SkipECCInit.JLinkScript and verify/add: // At the top of the JLinkScript file int InitTarget( void ) { // Explicitly declare big-endian JLINK_ExecCommand( &quot;SetEndian big&quot; ); // ... rest of ECC skip code return 0 ; } If the script does not contain this, add it as the first line of InitTarget() . Issue 3: Cannot Read Memory/Variables Without Halting This is a real-time memory access limitation with the J-Link on TMS570. Enable DAP-Based Non-Intrusive Access In CCS Debug Configuration under J-Link settings: Enable &quot;Non-intrusive (SWO/SWV)&quot; → Disabled (TMS570 doesn&#39;t support SWO) Enable &quot;Allow memory access during run&quot; → Check if available Alternative: Use ARMV7 DAP Directly In your .ccxml , try forcing the connection through DAP: Note: The TMS570LS1227 does NOT support true run-time memory access without the ETM/ETB infrastructure being configured. This is a silicon limitation, not a J-Link limitation. The XDS100V2 had the same restriction but handled it differently through TI&#39;s proprietary ICEPICK router. Issue 4: CCS Package Manager Failure / Manual DLL Replacement This is likely the root cause of several downstream issues . Proper Manual Integration Steps Rather than replacing the DLL directly (which causes version conflicts), do the following: Step 1: Install J-Link software from SEGGER separately Step 2: In CCS, go to: Window &gt; Preferences &gt; Code Composer Studio &gt; Debug &gt; GDB SEGGER J-Link Debugging Step 3: Point CCS to the installed J-Link directory explicitly: C:/Program Files/SEGGER/JLink_V798/ Step 4: Do NOT mix DLLs between CCS internal versions and SEGGER installed versions. Remove any manually placed DLLs from: [CCS Install]/ccs/ccs_base/DebugServer/drivers/ Recommended Complete Debug Configuration Connection: SEGGER J-Link Device: TMS570LS1227ZWT ← Verify exact part suffix Interface: JTAG Interface Speed: 1000 kHz (start low, increase after stable) JLinkScript: [full path]/TI_TMS570Lx_SkipECCInit.JLinkScript Reset: Core Reset Halt on connect: NO (for connect-to-running) Recommended Troubleshooting Sequence 1. Remove all manually placed DLLs from CCS directories 2. Reinstall J-Link V7.98 cleanly from SEGGER 3. Point CCS Preferences to the SEGGER install directory 4. Create a fresh .ccxml using CCS Target Configuration editor 5. Add SetEndian big to JLinkScript InitTarget() 6. Set Interface Speed to 1000 kHz 7. Disable all reset-on-connect options 8. Connect and check J-Link log for script execution confirmation If All Else Fails: J-Link GDB Server Approach Bypass CCS&#39;s J-Link integration entirely: # Launch J-Link GDB Server manually JLinkGDBServer.exe -device TMS570LS1227 -endian big \ -if JTAG -speed 1000 -scriptfile TI_TMS570Lx_SkipECCInit.JLinkScript # Then connect CCS to localhost:2331 via GDB This isolates whether the issue is CCS integration or the J-Link connection itself. -- Thanks &amp; regards, Jagadish.https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1686338/tms570ls1227-segger-j-link-usage-with-cortex-rWed, 30 Sep 2026 20:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8a0830c2-2c92-4fe8-b45a-7759f09aa04cJacob ByersPart Number: TMS570LS1227 Other Parts Discussed in Thread: CCSTUDIO Hello, I am shifting from the XDS100V2 to the Segger Jlink Pro (ethernet) for debugging, but am having some issues getting it working with CCS. I can connect to the debugger through CCS with no additional JLinkScript files used, but consistently get &quot;Break at address 0x0&quot; and cannot meaningfully debug without power-cycling the TMS570. Even so, I am unable to read memory or variables without pausing execution (as described here: TMS570LS1227 debug with SEGGER&#39;s JLINK - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums ). I&#39;ve followed the segger documentation for integration with Code Composer Studio, to include the inclusion of the ECC initialization skip script provided (see link below): TI Code Composer Studio - SEGGER Knowledge Base TI TMS570Lx - SEGGER Knowledge Base kb.segger.com/images/7/70/TI_TMS570Lx_SkipECCInit.JLinkScript I have used the V9.80 and V7.98 JLink Drivers with little discernable difference in outcome. When I specify the provided JLinkScript file that skips ECC initialization (to achieve my goal of connecting to the running target), I get a error that indicates a target endianness mismatch (this is not a true error). For transparency, I have been seemingly unable to add JLink through the CCS package manager. I get similar issues to here: https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/923260/ccs-adding-j-link-debugger-to-ccs I seem to have been able to get around this by replacing the dll directly in code composer studio with the up to date version from SEGGER. I (and several coworkers) tried this on CCS 10.4, 12.8, and 11.0 with similar results. Do you have any advice on how to proceed?CCSTUDIOTMS570LS1227Aerospace &amp; Defensehttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1681542/am2611-am2611-sysconfig-error-when-enabling-pru-icss-with-r5f-clock-configured-at-500-mhz/6498628Wed, 30 Sep 2026 16:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bb313b83-9afa-4c7f-b71f-7489a64b2620Shaunak DeshpandeHi Kalin, The details were shared offline with some colleagues at your company. Please let me know if this issue can be closed. Regards. Shaunakhttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6498458Wed, 30 Sep 2026 14:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:211308d8-48c0-4238-843d-475f7f70e733Sebastien Le DiourisHello Ella, now it works, but not because I have done your modification but because I changed the source clock, before I used SYSOCS and I changed by crystal (external clock) Thanks for your help, I close the topichttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6496616Tue, 29 Sep 2026 02:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:93789079-c4ec-4190-87c3-f72c19cef8d3Ella TangHi Sebastien, Regarding the ti_msp_dl_config.c and ti_msp_dl_config.h files, we can close the &quot;Include in build&quot; and save files to our project root folder, then we can modify the files directly. Like this: Thanks and Best Regards, Ella Tanghttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6495790Mon, 28 Sep 2026 12:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ceaf3c94-e6ab-4a57-b921-745a0790c6b7Sebastien Le DiourisHello Ella, yes I have MCAN_init, done before SYSCTL clock. But how do you do to not generate automatically the file &quot;ti_msp_dl_config.c&quot; ? thankshttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6495681Mon, 28 Sep 2026 10:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6152cbfd-2ef2-48df-8aa4-371727ae6110Ella TangHi Sebastien, We currently suspect a potential conflict in the initialization sequence. Could you please check inside the SYSCFG_DL_init() function? If SYSCFG_DL_MCAN0_init() is called before SYSCFG_DL_SYSCTL_CLK_init() , please swap their order to ensure that SYSCFG_DL_MCAN0_init() is called after the clock initialization. For example: Under this configuration, does the debug session still fail to work properly? If it remains stuck, what are the values of those registers at this point? Thanks and Best Regards, Ella Tanghttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6495665Mon, 28 Sep 2026 09:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ec578f23-a649-4e4b-a1f5-368c53196ff8Sebastien Le DiourisHello Ella, please find below the values Best regards Sebastienhttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6495607Mon, 28 Sep 2026 08:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c61a9a82-b9d2-4a5c-a529-3b08a7d90bbeElla TangHi Sebastien, Since this approach did not resolve the issue, let&#39;s revert the code back to its original state first to pinpoint the exact root cause. Then, please let the code run until it gets stuck, and export the hexadecimal values of the following four registers via the Registers window in CCS: CCR, PSR, ECR . For example: Thanks and Best Regards, Ella Tanghttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6495543Mon, 28 Sep 2026 07:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6540c43c-67d6-43df-b60f-87cfe0559e78Sebastien Le DiourisHello Ella, thanks for your response, but unfortunetly, it is not better Do you confirm you requested me to do this ? Thankshttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6495328Mon, 28 Sep 2026 02:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:712559f0-b99b-42e9-84d7-3331596c64e6Ella TangHi Sebastien, In SDK 1.4.0.00, SysConfig attempts to configure MCAN before the Message RAM initialization is fully complete. Consequently, the hardware state machine locks up, and getOpMode() gets stuck indefinitely in SW_INIT mode. So we can manually reset the MCAN0 module and add a startup delay in main.c before SYSCFG_DL_init() runs. Something like this: DL_MCAN_reset(MCAN0_INST); delay_cycles(16); DL_MCAN_disablePower(MCAN0_INST); delay_cycles(32); DL_MCAN_enablePower(MCAN0_INST); delay_cycles(4000); // Wait for Message RAM initialization, about 50us. If CPU frequency is 80MHz, the cycles are 4000. SYSCFG_DL_init(); Hope the method can resolve your problem. Thanks! Best Regards, Ella Tanghttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1681922/tms320f28377d-ccs-build-report/6495264Sun, 27 Sep 2026 22:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2a82adc1-cd6e-404b-84d4-6f6def9e1468Takayuki MoriHi, Ira Thank you for your reply. However, I cannot find the folder you mentioned. Could this be because I am using CCS version 20.2.0.12__1.8.0 rather than Eclipse? I would appreciate your further guidance. Regards, T. Morihttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684953/mspm0g3505-q1-trouble-writing-memory-block/6495203Sat, 26 Sep 2026 21:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:68657f6a-b17c-4e8a-a752-ab48bb66e0a5Brian LeeHi Alok, It sounds like the flash procedure is getting interrupted, causing the CPU to lock up due to an incomplete/invalid application image. Can you verify the MSP&#39;s power and nRST lines are high for the full programming duration and that the SWD signals aren&#39;t being interrupted? Additionally, can you run the Boot diagnostic read script in CCS? An output code of 0x7 would confirm the CPU has indeed locked up. Best Regards, Brianhttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684382/mspm33-sdk-sw-unfunctionning-after-changed-the-sdk-version/6494625Fri, 25 Sep 2026 12:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1fde6df4-15c2-407c-af03-f37bf3563b39Sebastien Le DiourisAny news ?https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1682990/mspm0g3519-compare1-timerperiod-cannot-set-to-32bit-max-0xffffffff---limited-to-16bit-0xffff/6494279Fri, 25 Sep 2026 00:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:18a3359c-44ce-43af-82dd-7f96b62b2207Satoshi KawaguchiThank you for handling this problem. I look forward to your response and receiving its resolution.https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684114/am3358-ccs-12-working-with-jtag-probe-xds200-to-trace-u-boot-and-vmlinux-based-on-am335-sdk/6493669Thu, 24 Sep 2026 13:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fbf4cc70-9efb-4498-b1db-fb9106ddcd3fTushar ThakurHi, Please refer to RE: SK-AM62: Code Composer Studio failed to connect to XDS 110 probe. for documentation details on debugging Linux SPL and u-boot in CCS. Regards, Tusharhttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684231/f29h850tu-f29h85x-recommended-way-to-assert-a-fault-pin-on-cpu-watchdog-timeout/6493609Thu, 24 Sep 2026 12:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:31f3a9f9-407a-466c-9abf-b727bc6f9320Alfred FreisingerMoved to C2000 forum, can be closed here. New link: e2e.ti.com/.../f29h850tu-f29h850tu-recommended-way-to-assert-a-fault-pin-on-cpu-watchdog-timeouthttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684231/f29h850tu-f29h85x-recommended-way-to-assert-a-fault-pin-on-cpu-watchdog-timeout/6493607Thu, 24 Sep 2026 12:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:82f78fa5-3ed0-4e43-a919-fde80b475926Alfred Freisingermoved to C2000 forum, can be closed. New link: e2e.ti.com/.../f29h850tu-f29h850tu-recommended-way-to-assert-a-fault-pin-on-cpu-watchdog-timeouthttps://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/1684953/mspm0g3505-q1-trouble-writing-memory-blockThu, 24 Sep 2026 09:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a568fa23-e189-4a61-8cfc-f0e4cfc79df3Alok BardhanPart Number: MSPM0G3505-Q1 Hello, I am trying to flash a custom board having a SBC(TLE94613ESV33XUMA1) connected to the microcontroller(M0G3505QRHBRQ1) via SPI which drives two LED drivers(MPQ3324GRE-AEC1-P). The SBC has a watchdog, so for the very fisrt time when I am flahing the G3505, I supply 3.3V to Test pin 10 ensuring the watchdog is disabled during flashing. However, in many scenerio I get this error &quot;[9/21/2026, 1:54:51 PM] [INFO] CORTEX_M0P: GEL Output: Memory Map Initialization Complete[9/21/2026, 1:54:52 PM] [ERROR] CORTEX_M0P: Trouble Writing Memory Block at 0x2288 on Page 0 of Length 0x8: Flash download failed! ...[9/21/2026, 1:54:52 PM] [ERROR] CORTEX_M0P: File Loader: Verification failed: Target failed to write 0x00002288 &quot; And after that I am not able to connect the target and getting this error &quot; [9/21/2026, 1:54:56 PM] [ERROR] CORTEX_M0P: Error connecting to the target: Could not connect to target.[9/21/2026, 1:55:00 PM] [ERROR] CORTEX_M0P: Error connecting to the target: Could not connect to target. &quot; Why the flashing is failing, could you please provide some support?MSPM0G3505-Q1Body Electronics &amp; Lighting