I changed a number of parts to custom components, the main one being the output capactor. I need a long hold up time in my circuit so I wanted to see how this would work. The part in question is the TPS54060-Q1. I set the output capacitor to 3.9mF with 12mohms of impedance Rcomp to 1MEG, Ccomp to 1nF Ccomp2 to 1pf. The chart showed fairly good phase margin once I tweaked the feedback, but now that I want to see what that looks like the simulation fails.
I am wondering if it fails because I have played with the circuit too much? If the simulation fails, can I rely on the phase margin graph for the loop response?
Vin 18-60V
Vout 14.3V
Iout 0.1A
Your simulation failed due to a netlist error. If you recently changed a component in the BOM or changed a simulation related parameter, try changing it back to its previous value. If the problem persists, it may be due to an internal problem in our system. The problem has been logged and the development team has been notified. If you have any questions, please submit a feedback online at http://webench.ti.com/support/.
Error File Contents:
Simulation: FAIL
* ERROR * cir.pspice[138:8-138:8] - Syntax error. Unexpected token: character (PARSER-2)
* ERROR * Parser error... bailing out. (PARSER-1001)
**************** ERROR/WARNING COUNT ****************
**************** ERROR/WARNING COUNT ****************
Type: PARSER #errors: 2 #warnings: 0
--TOTAL-- #errors: 2 #warnings: 0
Status = Fail
FAILED SIMULATION
failed
simStatus=Failed