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TIDA-00204: BSP sources

Ildar Sadykov
Prodigy 120 points
Part Number: TIDA-00204
Other Parts Discussed in Thread: TMDSICE3359

Hi

Our hardware engineers used TIDA-00204 Schematic as a reference to use DP83867 PHY with AM335x MPU.

So I'm trying to find some Software samples which can help me up RGMII Interface Sitara=>DP83867.

But, unfortunately, on Board's page http://www.ti.com/tool/TIDA-00204 I found only ZIP archive with prebuilt MLO and App images.

Where can I found examples for U-Boot (such as AM3358EVMSK files pinmux.h, mux.c, board.c) and Linux (.dts settings)?

Thanks!

  • 0
    TI__Expert 7840 points
    Due to licensing agreement, we cannot provide the specific source code used for the TIDA-00204 board.

    To understand what public released SW was used to develop the tida-00204 binary a specific software section “3.1.2.2” was added in the design guide, where you can find which public released Sitara SW was used in the TIDA-00204 design.

    The software examples used from the public release are based on the EVM TMDSICE3359.

    Here please notice that the software used have newer releases available.

    On questions on the public released Sitara SW, please go to the Sitara forum:
    e2e.ti.com/.../
  • 0
    Prodigy 120 points

    Just for information.

    Valid davinci_mdio device tree config for my "TIDA-like" board (delays may be wrong, because of now I operate only at 100Mb speed):

    &mac {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&cpsw_default>;
    pinctrl-1 = <&cpsw_sleep>;
    dual_emac;
    status = "okay";
};

&davinci_mdio {
    pinctrl-names = "default", "sleep";
    compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
    pinctrl-0 = <&davinci_mdio_default>;
    pinctrl-1 = <&davinci_mdio_sleep>;
    status = "okay";

    dp83867_0: ethernet-phy@0 {
        reg = <0>;
        ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
        ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
        ti,min-output-impedance;
        ti,dp83867-rxctrl-strap-quirk;
    };

    dp83867_1: ethernet-phy@16 {        

        reg = <16>;
        ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
        ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
        ti,min-output-impedance;
        ti,dp83867-rxctrl-strap-quirk;
    };
};

&cpsw_emac0 {
    phy_id = <&davinci_mdio>, <0>;
    phy-mode = "rgmii-id";
    dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
    phy_id = <&davinci_mdio>, <16>;
    phy-mode = "rgmii-id";
    dual_emac_res_vlan = <2>;
};