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Part Number: TIDA-00774
recently I design a prototype with DRV8323RS and take the TIDA-00774 eval board as a reference. I have a question on the functionality of the two Decaps across each inverter leg.
I am not sure why we need these Decaps here. If we want to have a relative constant PVDD, then Decap between PVDD and GND is more reasonable.
My explanation so far is only, it works as a snubber, to suppress the switching current.
Could someone help me out of this confuse? Thanks in advance.
The Decaps between the PVDD and GND will help only in the PVDD supply filtering. The decaps across each inverter leg helps in clean FET switching with reduced voltage spikes or oscillations. The common source inductance for the low side FETs, which is contributed by the current sense resistor and the low side tracks is a common concern, which can create switching oscillations at the source pin of the low side FET, which further create oscillations in gate voltage and the VDS. The decaps across PVDD and GND will not help here as these cap AC current loop includes the sense resistor and hence the high common source inductance. Therefore it is recommended to use a small value capacitor exactly across each inverter leg to get the best performance. The value could be very low (10nF), but the placement is critical. It should be direct and as close to the FETs. One thing should be noticed that this cap will slightly filter out the peak current appearing in the shunt resistor.
Thanks & Regards,
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In reply to Manu Balakrishnan:
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