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Original question:

TIDA-00951: TIDA-00951

TIDA-00951: TIDA-00951 Design Errors

Guillermo Perez Vazquez
Prodigy 185 points

Part Number: TIDA-00951

Hi TI,

We are having problems with the reading of the ADC channel whta comes from the VBUS voltage level. And we have found two different versions of the accomodation signal circuit from VBUS point to the ADC B6 channel. The question is, what is the correct between these two schematics?

1) Circuit shown on the PDF of the TIDA-00951 section 6.3.1.7 Isolated Voltage Sensing: http://www.ti.com/lit/ug/tidud04/tidud04.pdf 

2) Circuit shown on the SCHEMATIC of the TIDA-00951 Sheet 3, and for that, the final ALTIUM project and physical PCB: http://www.ti.com/lit/df/tidrr65/tidrr65.pdf 

We are reading always in Code Composer the same value in bits (Saturation): 4095 no matters the voltage in the pin VBUS of the power circuit.

- Regarding the last issue about the VBUs signal conditioning with the AMC1301 and the OPA276 circuit, both versions (TIDA-00951 and Altium files from your product website) are wrong.

We have simulated both versions of the circuit in LTSpice and none of them works as espected, so we have searching on different application notes related to the AMC1301 and OPA376 as an isolated signal conditioning and we have found the right configuration, which works fine in LTSpice. This circuit is shown below:

- Because we have the manufactured PCBs and the software already running in the LAB, your proposal needs a Hardware modification in the PCB project, etc. Anyway, your circuit proposal doesn't work in simulation as we spects for that signal conditiong of VBUS.

- We have implemented in the PCB another version connecting +1.2V offset voltage in the R68 pad. And now we have got good results at testing LAB:

Please, let us know your thoughts about it.

Have a nice day,

Regards, 

Guillermo Perez

  • 0
    Prodigy 185 points

    Dear Ram,

    The circuit you proposed for the VBUS sensing saturates its output too early, I  have simulated your proposal. See the attached picture:

    We have implemented this circuit and it shows better response both in simulation and in real Hardware testing:

    What do you think?

    Thank you

  • 0 in reply to Guillermo Perez Vazquez
    TI__Intellectual 2815 points
    Hi Guillermo,

    Reposting my reply from the other thread.


    The R7 and C3 need to connected to the +ve input terminal of the opamp in the first simulation that you showed.

    Adding a 1.2V offset in the 2nd simualtion is not a problem as such. It will result in an ADC ofset of +1.2V at 0 input voltage on the BUS.



    In the cirucit 1 simulated with the changes I suggested in this post, you should be able to elimiante the offset. The TIDA-00951 firmware will expect close to 0V offset at 0V Bus input, unless you change it accept a 1.2V offset.



    Best Regards,

    Ram
  • 0 in reply to Ramkumar S
    Prodigy 185 points

    Hi Ram,

    The circuit I have simulated is the same that you proposed me, with R68 and C76 in the V- pin of the Amp Op:

    Hi Guillermo ,

    Please use the schematic snippet attached with this mail. I will send you an email with the DNP parts toady.

    Best Regards,

    Regards,

    Guillermo