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TIDA-01573: How can guarantee the fast turnoff speed of the Laser Diode

Part Number: TIDA-01573
Other Parts Discussed in Thread: LMG1020,

Hello,

I want to know when place a Schottky diode paralling with the laser diode,how can  guarantee the fast turnoff speed of the Laser Diode.Because when the GaN turn off, the Schottky diode turn on,the voltage applied on the LD is very small,so I think LD may not turn off quickly.

  • Hi User,

    thanks for your question on LMG1020 and TIDA-01573 and welcome to e2e!

    An anti-parallel diode can be added to clamp the drain voltage of the FET to the supply so that when the FET turns off, the high peak current flowing in the stored parasitic inductance has somewhere to go and does not cause FET drain over-voltage. The anti-parallel diode can contribute to longer laser rise and fall times as well as FET over-shoot and decreased efficiency. To keep the turn on time as short as possible while using an anti-parallel diode, the diode capacitance needs to be small relative to the laser diode capacitance since it needs to be charged during turn on. To keep the turn off time as short as possible while using an anti-parallel diode, make sure the parasitic inductance of the layout and leads of the diode relative to the laser are smaller and as close as possible so that most of the laser current during turn off will flow through the diode and not into the drain of the FET. To achieve a faster fall time of the laser diode also make sure the leads of the laser diode are as short as possible and your scope/probe can achieve GHz high-frequency measurement. Does this help answer your question? for more details on this please check out section 2.2.7 of TIDA-01573 http://www.ti.com/lit/ug/tidue52/tidue52.pdf

    let me know if you have any more questions,

    thanks,

  • Hi Jeffrey,

    thanks  for your answer.Can I understanding your reply in the way below? If the  parasitic inductance of a LD is not so small,such as 1nH,and I want to turn off the LD in 2ns at the peak current 50A. I can easily know that a voltage of 25V should be applied on the LD. But due to the existence of the clamping diode,it's impossible because the forward drop voltage of the clamping doide is very small.So if I want to use TIDA-01573 to drive a LD,the LD's parasitic inductance must selected strictly. So the way TIDA-01573 using is not appropriate for LD with not so small parasitic inductance and it's not popular. Am I right? Looking forward to your reply.

  • Hi User,

    thanks for your reply,

    this is correct L*di/dt tells you that 25V drop will occur across the 1nH LD during a 2ns turn off. The clamp should limit this to 5 or 10V. In order to reach 50A of peak current the LD should have a small inductance. SMD LD will help lower the inductance. If using a 2 terminal leaded LD make sure the LD leads are small to lower inductance. A 3 terminal LD is recommended to make use of the split power plane described in section 2.2.5 of the TIDA. Please let me know if this makes sense and answers your questions?

    thanks,