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TIDA-01573: operate low voltage

Yuki Ashida
Prodigy 20 points
Part Number: TIDA-01573

Hi,

Is it possible to use the low voltage Laser Diode?

I actually want to use sony SD3236VF.

This one is 150mW and operating at 5.3-5.5 V.

You suggest the input voltage within 30-75V, but does it have a chance to use it?

Thank you,

  • 0
    TI__Expert 3355 points

    Hi Yuki,

    I work on the applications team in the high power drivers group and can help you with your question.

    This reference design can switch 5.3V-5.5V with no issue.

    A quick tip though: Depending on your pulse width, you probably won’t get your desired peak current pulse when switching with only 5.5V on the bus. With a fixed pulse width, your peak current is limited by the parasitic inductance in your LED drive loop.

    V = L*di/dt

    Rearranged: di = V*dt/L

    di is the desired peak current, dt and L are usually fixed by the system requirements and layout, respectively.

    In order to increase the peak current, you must increase the switch voltage which is switched onto your entire drive loop. The laser diode keeps following its VI curve, and only experiences a small part of the total switch voltage, while the rest of the voltage is dropped over the parasitic L and FET Vds.

    If this answered your question, could you please press the green button? If not, please feel free to ask more questions.

    Thanks and best regards,

    John

  • 0 in reply to John Geiger
    Prodigy 20 points

    Hi John,

    Thank you for your quick response!

    And your tip is very helpful.

    I actually changed a setting of the pulse width from 100 ns to 200 ns.

    I then get a laser pulse, but it has a wide pulse width such as 25 ns.

    It seems to relate an input pulse width.

    Does it mean that we need a 1 GHz pulse generator to get a 1.x ns pulse width?

    Would you let me know if you have any idea to generate reasonably such high freq. pulse.

    Thanks again!

    Yuki

  • 0 in reply to Yuki Ashida
    TI__Expert 3355 points

    Hi Yuki,

    This reference design includes a pulse-width reduction circuit using an AND gate to aid in achieving these very narrow pulse widths. I think that you understand that the input pulse width needs to be adjusted with very fine resolution. We typically use dedicated function generators with very fine pulse width control for our testing. If you are using an FPGA to generate the input signal, then you will need to synthesize a variable duty cycle circuit to achieve higher pulse width resolution.

    I’m not very experienced with this type of design but, for example, you might synthesize a phase delayed clock signal from your reference clock, and a comparator to compare these two clocks. The output pulse width would be determined by the phase difference between the two clocks. There are a variety of papers out there which might help you come up with more ideas for this adjustable pulse width circuit.

    If this answered your question, could you please press the green button? If not, please feel free to ask more questions.

    Thanks and best regards,

    John