TIDA-01505: Reference design calculations

Hi,

I agree there appears to be some typo's in the first couple of items you listed in the TIDA. I will track down the design engineer and as ask him to respond to your questions.

Regards

Peter

Hi Smitha,

Thank you for your questions regarding this TIDA. Please see my answers below the lines.

1. In the reference design calculation of TIDA-01505 for startup circuit below are the observation and wanted to know how does it worked for you.

1. values arrived in the equations (37) for startup current is wrong. Startup current should be 102.6 mA but mentioned as 0.103mA.
2. Hence the collector resistor calculation of Darlington Pair should not be 314Kohm (as written in Equation (38). Rather it should be 314Ohms
3. In the equation (39), IC_max =3.1A is calculated correctly (by taking 314ohms as said in the point (b) above).
4. Ic_max is specified in the datasheet of Darlington Pair transistor STP03D200 is 100mA. But calculated Ic_max in point (C ) above is 3.1A. How does transistor survive this huge current.
5. In equation (40) the power dissipation is calculated with 3.1mA which is wrong it has to be 3.1A. Hence power dissipation comes hypothetical for a 60W power supply design.

Can you please share the calculation and values of startup circuit which has worked for you in lab testing described in figure (14) in the reference design TIDA-01505

Thanks for pointing these out. Some errors occurred when transferring all the equations to  the final documentation. We did the final tuning in the Lab. The fast lane startup are reduced to 15k. You are right it needs to limit the Ice current below 100mA maximum. Sorry for the confusion.

Does startup circuit works for entire range 40V – 1000V or it works for a specific input voltage.

It works for the entire range of 40V to 1kV.

1. With the external voltage source (VDD) of 16V @ >80mA MOSFET C2M1000170D  works fine. But for current<80mA, MOSFET is loading the VDD supply and PWM controller goes to UVLO mode and hence disabling PWM. We tried to increase the VDD capacitance from 22uF to 270uF. But it didn’t help.

 Try to reduce the switching frequency to ~80kHz. This helps to decrease the instant current.

1. We have seen few SiC MOSFET - C2M1000170D failure and observed Gate and Source showing short. Did you also faced similar issues. At full load conditions & higher voltage ~ 950V SiC MOSFET has failed. Can you help in resolving this issue.

 We didn't observe this issue. Try to reduce the bias winding voltage from +20V to +18V.

1. In the datasheet of PWM controller UCC28C43-Q1 transfer function arrived in equation (53) doesn’t include the type 2 compensation (see below image) while the reference design TIDA-01505  include type 2-compensation. Can you provide the transfer function to check the stability.

      The type 2 provide additional zero. The component values are turned and optimized in the lab. 

1. In the below image, VDD connection to Totem pole is given directly from unregulated voltage from Transformer Auxiliary winding. Is this purposefully done as shown in below figure (red color) . Or it should have been connected to regulated supply as shown in figure(green color).

Either would be ok. depending on the drive voltage you want to give to the SiC MOSFET.

1. In the reference design TIDA-01505 under the slope compensation network, Rramp (R71=9.09kohm). But its suggested to choose this resistor value higher than the value used in RT resistor (R60 =13K) as per section 2.3.11.1 (between equation 54 & equation 55). Refer the below image:

The condition needs to be meet without the emitter follower by Q15. With the emitter follower it is not required.

1. We have chosen EF25 (N87 grade) transformer for the design to meet the board dimension requirement

For transformer design, needs to pay attention on the inter winding capacitance. It needs to be minimized as low as possible to avoid false triggering on the CS.

Hello Xun,

Thank you for the quick response.

I have few more queries for better understanding

• As mentioned by you the fast lane resistor value is 15k. Which means the Ic current with min and max input voltage would be 2.16mA and 66.16mA respectively which would be <100mA rated current of the Darlington pair transistor. Hence this should be Ok. Assuming 6 instances of 2.5k each, the power dissipation would be around 10W (66.16mA^2*2.5k) which is huge, What is the package selected in the design to meet power loss?
•  Could you please share the slow lane resistor values also,  because even there the problem would be power loss which is even more higher than the fast lane.
• What does the terms slow lane and fast lane define? Does fast lane means circuit without Darlington transistor?
• What is the operating frequency of your final design? Is it 80kHz or 140kHz. Because with lower frequency transformer size would increase. Please confirm.
• Your comment : “Try to reduce the bias winding voltage from +20V to +18V”. But this should not be a problem as Zener diodes are placed to protect the gate of the SiC MOSFET.
• Could you please provide the final values of type 2 compensation network which worked for you in Lab. Is it the same which is mentioned in the reference schematic?
• Regarding the VDD connection which you mentioned both would be ok – How does the totem pole turn on during startup with the connections shown in the reference design
• In the below image (CH1: MOSFET Gate; CH2 : PWM IC Output; CH3: MOSFET Drain current, CH4: Drain to source voltage) it is observed that even though PWM IC output is continuous, PWM at gate of the MOSFET is not continuous, the gate sees the pulses only for certain duration and does not see any gate pulse for few more cycles (where PWM IC Output goes to minimum duty cycle). Any reason for such behavior?
  
  
  

Hi Smitha,

The fast lane is referred as  the low ohmic resistors chain without Darlington transistor. This resistive chain only conducts current during start up before the +20V appears. Then Q9 will be turned off and block the current, it will not consume power any more. The higher the input voltage is, the shorter the startup time is. Therefore you don't need to consider such high power consumption. 

The operating frequency is 140kHz. But as you are experiencing a big voltage drop on the Vdd pin I recommend to reduce the switching frequency, which reduces the Vdd pin capacitor loading. 

The final values of type 2 compensation network are the same as shown in the reference schematic.

In the case of connecting collector of TTPL to the +20V line as shown in the reference design, the +20V line needs to be connected to an external power rail.

In which condition these waveforms are measured?

Hello Xun,

Thank you for the information.

• The above waveforms were measured with load (~0.2A) at Input voltage of 200V. If we go for load of more than 1A there is no issue observed, i.e the waveform is continuous.
• Please share the values that are kept for slow lane resistor in the final design
• So are you using external power rail of +20V and -5V for TTPL logic in your design.Please confirm
• Do you have any updated schematic after the lab testing. Please share.

Regards

Smitha M S

Hi Smitha,

The final value for the slow lane resistor is 49k in total. Yes, the +20V and -5V is applied externally. I don't have an updated schematic. The schematic on the web is the latest one. The final change would be fine tune the startup resistors to meet the stratup time need accordingly.

From the waveform it seems the spike on the CS pin is pretty high. The current limit is triggered and the IC goes to protection. 

Hi Xun,

Regarding Slow Lane resistors, does that mean the total series resistance of R37+R39+R41+R44+R48+R49 should be 49K rather than 9MOhm ( 1.5M x 6 ) as in the present schematic ? Also when the 9MOhm is replaced by 49K, the current will be ~20.4mA at 1000V when Q10 is ON which is the normal state after startup when +20V is present? With this current, the total power dissipation on the 49K resistor will be ~20W. Even if divided in 6 resistors, this would be ~3.33W on each !!!.

Regarding Fast Lane resistors, does that mean the total series resistance of R38+R40+R42+R43+R45+R46 should be 15K rather than ~300K as in the present schematic ?

Are these two the only final changes from the present schematic? ( Schematic referred is updated on July 09, 2019 ) ?

Regarding +20V & -5V, if the Transformer has auxiliary winding which provides +20V & 5V ( as WA8759-AL in Reference Design ) do we still need to supply these rails externally?

Hi Smitha,

The 37+R39+R41+R44+R48+R49 remain the same 9MOhm and no change, change the R38+R40+R42+R43+R45+R46 to be 49k in total. We also reduced the R38+R40+R42+R43+R45+R46 down to 15k to further increase the startup time. Therefore no huge power consumption occurs.

These two are the only changes. Yes, you need to have external supply externally during start up if the level shifter is connected to the node of R80. If you connect the R58 to the VDD node, the level shifter will take the power from R38, R40, R42... resistive chain during startup phase. Then you don't need external power supply. You might need further decrease the resistive values to increase the startup power. The level shifter requests the voltage being present first in order to drive the MOSFET properly. 

Hi Smitha,

Since there has been no activity on this post for a number of days now I assume Xun has answered all your questions.

I will close this post and please open a new post if you have more questions.

Regards

Peter