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Part Number: TIDA-01604
How to determine the grid frequency in reference design TIDA-01604? I only see the phase-locked section in the reference manual.
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In reply to F.F:
Because the software need change low frequency SR switch and main switch, so there will have zero cross detect. you can get the frequency from two zero cross time. But i don't understand why using spll there, the current ref can get from Instantaneous Vac，you know ,spll need amount of calculation.
In reply to user4584317:
1. The PLL was added to provide the following
a. It allows for vector based cancellation techniques for power factor improvement
b. It adds robustness against noise which can also result in wrong changes to the totempole bridge
The phase locked loop provides a frequency output as well, but it will change wuite often as it is also used for the lock. You may have to add some aditional filter on it. In addition to that the sine analyzer also outputs frequency information from the zero crossing information.
In reply to Manish Bhardwaj:
I've heard so much about you, thank you for your reply! But i have some questions:
1:what's the meaning of "vector based cancellation techniques". why use spll' result sinQ instead of instantaneous ac voltage?
2:can i get frequency from pll? i think it just lock the phase, it is not fll.
I am looking forward to your reply.
1. We published a paper here
Also it is covered in the UG for TIDM-1007 which is a lower power version of the same topology see
2. Please see the module
float32_t fo; //!< Output frequency of PLL(Hz)
f0 is the output frequency, but you will need to put a low pass filter on it as it will oscialte due to PLL action.
How fast does the frequecy read needs to be ? Can it tolerate some latency?
Thank you very much for your reply. I have benefited a lot from it
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