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TIDA-01480: Ramp times?

Tom Schultz
Expert 3665 points
Part Number: TIDA-01480
Other Parts Discussed in Thread: LM3881

Hello,

I'm posting on behalf of my customer.

We are analyzing the FPGA’s XCZU3CG,  XCZU4CG and XCZU5CG for this project.  I took the power sequence from the  Xilinx DS 925 Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics and currents from the XPE spreadsheet. Our Current values are higher than what is seen on TI's processor power webpage for the same model.  Our project  calculation is near 0.85V/10A and 1.8V / 1.5A.

       My power system is based on the TIDA 01480. I have concerns regarding the necessary time between the power sources energizing/ramping up.  I have the ramp of each power source, but not the information of any necessary wait time between the activation of each power source. Or if I can activate each power source after the subsequent power source, just respecting the ramp time.

Aside from the rail sequencing, can you let me know about the timing specifications for each supply in TIDA-01480?  How are the individual ramp times factored in here?

Thanks,

Tom

  • 0
    TI__Mastermind 30260 points

    Tom,

    Good question. Xilinx does not specify a delay between the rails during sequencing. However, our PMICs that sequence automatically typically have a delay of 2ms in between each rail. 

    The delay can be arbitrary, as long as the previous rail ramps most of the way (90%) before the next rail starts to ramp. The maximum ramp time is 40ms, so theoretically each delay could be this long although it is probably not necessary.

    The minimum number of rails that need to be sequenced is 3, according to the document you referenced (Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics)

    1. VCC_PSINTLP

    2. VCC_PSAUX, VCC_PSADC, and VCC_PSPLL in any order or simultaneously.

    3. VCCO_PSIO

    For 3 channels, the LM3881 is commonly used to sequence the rails and set the timing. If you wanted to sequence up to 9 rails, you could use 4 LM3881 devices (the 1st LM3881 is enabled by the input voltage, then the FLAGs 1-3 enable the next set of 3 LM3881 devices). I know this sounds a little complex, but it is the only implementation I know of that avoids using an MCU to sequence each rail.

  • 0
    TI__Mastermind 30260 points

    Tom Schultz said:
    Our project  calculation is near 0.85V/10A and 1.8V / 1.5A.

    For TIDA-01480, the main 0.85V rail is rated for up to 12A (usually VCCINT) while the auxiliary 0.85V rail is rated up to 8A (usually VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR).

    The 1.8V rail (VCCAUX, VCCAUX_IO, VCCADC, VCC_PSAUX, VCC_PSADC, VCC_PSDDR_PLL) is rated for 1.2A while the auxiliary 1.8V LDO (VMGTAVCCAUX (GTH), VMGTAVCCAUX (GTY), VPS_MGTRAVTT) is rated for for 200mA. In addition, there is a 1.0A supply for VCCO_PSIO[3:0] that is labeled with a voltage of 1.8V-3.3V because the different banks of IO can be powered from multiple voltages. So that total amount of current at 1.8V could be 2.4A

    I hope this explains the thought process of TIDA-01480 a little better.

    I cannot explain the logic which drives the ti.com/fpga processor power tool, except that I know they used the Xilinx Power Estimator (XPE) to do some rough estimates. Obviously, it is much lower than the high-end requirements of the ZU5CG device.