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Part Number: TIDA-010016
Tool/software: Code Composer Studio
meanwhile I have succesfully integrated the IO Link Master firmware at a new project.
Next big step will be to prepare the move from idkAM437x Eval target to own hardware.
Therefore I have checked the Pin assignment. I haven't found an IO-Link PinMux file.
Is this available?
Checking the signal pins within code, I found that GPIO4_14 is assigned (and/or commented ?) twice at IOLink_GpioInit() function.
And gpioPinConfigs structure contains 2 output pins for AM437x_IDK_YEL1_LED. Can you clarify this?
I think there is no dedicated document out there, clarifying the complete pinout.
For IO-Link there are basically two relevant parts, one is the IO-Link RX, TX and TX_EN lines that go from the SoC to the TIOL111 transceiver. These pins are PRU pins and need to be as assigned in the PRU code. You find this in the defines.inc in the PDK folder (pdk_am437x_1_0_14\packages\ti\drv\iolink\firmware\icss_iolink\src\include\io_link_master).
Here is a copy of this:
;RX and TX pin definition
;GPI / GPO pins of the PRU (R30)
;these pins are much faster as GPIO pins and can be written in a single PRU cycle
.asg "0", rx0_pin ;N24 J16 Pin 31
.asg "1", rx1_pin ;N22 J16 Pin 33
.asg "2", rx2_pin ;H23 J16 Pin 35
.asg "3", rx3_pin ;M24 J16 Pin 32
.asg "4", rx4_pin ;L23 J16 Pin 34
.asg "5", rx5_pin ;K23 J16 Pin 36
.asg "6", rx6_pin ;M25 J16 Pin 52
.asg "7", rx7_pin ;L24 J16 Pin 54
.asg "8", tx0_pin ;B1 J16 Pin 56
.asg "9", tx1_pin ;B2 J16 Pin 37
.asg "10", tx2_pin ;C2 J16 Pin 38
.asg "11", tx3_pin ;C1 J16 Pin 58
.asg "19", tx4_pin ;bluewire Pin 5
.asg "12", tx5_pin ;bluewire Pin 53
.asg "13", tx6_pin ;bluewire Pin 55
.asg "18", tx7_pin ;bluewire Pin 57
The next relevant pins are the TX_EN signals that are defined in the IOLINK_memoryMap.h:
/* TX enable GPIO port hw address */
#define channel0TxEnGpioAdr (0x48320000U) // this is GPIO4
#define channel1TxEnGpioAdr (0x48322000U) // GPIO5
#define channel2TxEnGpioAdr (0x48322000U)
#define channel3TxEnGpioAdr (0x48322000U)
#define channel4TxEnGpioAdr (0x48320000U)
#define channel5TxEnGpioAdr (0x48322000U)
#define channel6TxEnGpioAdr (0x48322000U)
#define channel7TxEnGpioAdr (0x4804C000U) //GPIO1
/* TX enable GPIO pin configuration */
#define channel0TxEnGpioPin (1U << 10U)
#define channel1TxEnGpioPin (1U << 4U)
#define channel2TxEnGpioPin (1U << 6U)
#define channel3TxEnGpioPin (1U << 23U)
#define channel4TxEnGpioPin (1U << 12U)
#define channel5TxEnGpioPin (1U << 26U)
#define channel6TxEnGpioPin (1U << 25U)
#define channel7TxEnGpioPin (1U << 8U)
And the last part, the IOs for the L+ highside driver for enabling and diagnostics you have already found in the gpioPinConfigs structure.
GPIO4_14 should only be configured once and is configured in gpioPinConfigs.
/* Output pin : TPS4H160 H_SEH 18*/ GPIO_DEVICE_CONFIG(4u + 1u, 14u) | GPIO_CFG_OUTPUT
Which PDK version are you using, so I can check this?
You are right, the comment for AM437x_IDK_YEL1_LED is duplicated. This seems to be a copy/paste mistake.
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In reply to Steffen Graf70:
I am working with pdk_am437x_1_0_15. Thanks for your quick reply!
In reply to Thomas Kuhnt:
thanks for this information. One of the entries with AM437x_IDK_YEL1_LED is actually this LED connected to GPIO4_16. The second entry is GPIO3_1 which connected to the SN65HVS882 LD pin. This is not used in the IO-Link example.
The duplicate GPIO4_14 comment is related to the high side switch (file ioLink_powerSwitchTask.c line 333 and 336). GPIO4_14 is connected to one of the select lines for diagnostics. In the second entry should be commented as GPIO4_15 and is connected to one of the fault pins.
I'll try to get this corrected in the PDK, thanks for pointing that out!
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