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TIDA-01480: Questions about startup

Part Number: TIDA-01480
Other Parts Discussed in Thread: TPS65023
Hi Team,

I have a customer with some questions about the TIDA-01480

I cannot understand how exactly the circuit starts. I have prepared a diagram of the TIDA again (so this is an exact equivalent from TIDA-01480):


VIO is the most important voltage when starting, as this voltage is used to generate the power sequencings.
At the same time, this voltage is controlled via the seq signal EN_SEQ_LDOA - or initially blocked!? 
I don't understand this loop - the output of LDO2 is directly connected to its own enable input. (Sheet2 are pure wire connections) The reset button S1 could still play a role, but according to data sheet TPS65023 it only affects the VDCDC1 output.   An important question is whether the TIDA-1480 board starts at J7 without an FPGA board docked?


Regards
Mihir
  • Mihir,

    You can pull-up EN_LDO to VSYS.

    You are correct: not all of the EN signals can be pulled up directly to VIO. Whichever rail needs to turn on first should have the EN pin pulled up to the input supply.

    I agree with you that it appears LDO_EN for TPS65023 is pulled up to its own output, and this obviously does not make sense. If an LDO is going to be used to power an MCU which will then use GPIO to enable the rest of the rails, then this LDO_EN pin should be pulled up to VSYS instead of VIO.