Hello,
the output capabilities of the LDO2 are <200mA. From TIDA-050000 i see this output provides the source for FPGA I/O Banks.
The Spartan 7 datasheet mentions a Power-On current of (Ivcco (4mA) + 40mA per Bank) * 7 = 308mA (For XC7S100 here).
I know this could be lowered with sequencing but isnt that very tight calculated or am i thinking something wrong here even on normal operation with DDR3 and Ethernet MAC running the same time 200mA is not enougth ??
The I/O voltages VCCO[0...] are actually connected to DCDC1 and DCDC3 as a primary supply for higher current, shown with dotted lines in the below diagram.
Although DCDC2 = 1.8V and DCDC3 = 2.5V, you could also set DCDC3 = 1.8V if 2.5V I/O voltage is not required.
LDO2 is just shown as another optional supply for some IO.
When you generate the XPE for your design, it will list all of the required power supplies and expected current consumption. This, in addition to the datasheet for your DDR memory and Ethernet PHY will tell you the power budget for each rail. TIDA-050000 is intended to be modified as needed for each different Xilinx application.
