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PMP8740: TIDA-00779 and PMP8740

Part Number: PMP8740
Other Parts Discussed in Thread: TIDA-00779, , PMP8790, LM5170, UCC28950, UCC28951, LM5170-Q1

Hi,

Can We use TIDA-00779 (3.5-kW PFC board) to power the DC-DC converter board of PMP8740?

The switching frequency used in TIDA-00779 is 40kHz whereas the DC-DC converter part of PMP8740 uses 100kHz.  Will it cause issues?

Awaiting response...

Regards,

Anbarasan R

  • Hi Anbarasan,

    There is no problem using the TIDA-00779 to supply the DC/DC converter of the PMP8740. Please consider that I supplied this DC/DC section with 400V and not 390V, so I suggest to increase the output voltage of TIDA-00779 accordingly.

    Regarding the switching frequency, 40KHz and 100KHz are far away to create a beat frequency in the audible range, so also from this point of view there is no issue.

    Best regards,

    Roberto

  • Hi Roberto,

     

    Thanks a lot for your input.

    I have few more queries listed below:

    • PMP8790 is designed for battery charging applications. However, we want to use it to power a motor load via INVERTER board. The load on the motor ramps to its maximum power in 2s. Should we change the compensation loop. 
    • In UCC288950, 600W design document -The controller goes into DCM mode at 15% load. Valley switching  below 50% load. My understating is the controller will realize the DCM mode by the voltage (Vrcs) set using the resistive divider (Which in turn depends upon the load). After which it goes into DCM mode from CCM mode and it will operate in valley switching to maximize efficiency.  But the % used for DCM and valley switching are different. Please comment on this.
    • We also aim for a current sharing between PMP8790 and LM5170EVM board. The LM5170 supports the PMP8790 during peak loads. Our plan is to use the PMP8790 as a voltage source and LM5170EVM board as a current source.  Will it work? Please suggest.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    You are referring to the PMP8790 here, but this reference design is an Active Clamp Forward converter:

    Is it a typo and you are still referring to PMP8740? If so, there is no issue to use the PMP8740 as a normal power supply, because it´s suitable for both tasks, charging batteries and supplying loads. In fact, even though the voltage loop bandwidth is comprised in the range 100 Hz .... 500 Hz, there is no problem supplying a motor that ramps up in 2 seconds.

    The PMP8740 is designed to work in parallel with other modules, or other power stages, so I think it can work also together with the LM5170 EVM.

    Now the UCC28950 EVM:

    The "valley mode" for this topology is actually the boundary between full ZVS and starting the hard-switching region. This boundary is dependent on the leakage inductance of the transformer+ the shim inductor. The energy stored in these two magnetic components are driving up and down the switch nodes of the main FETs. When this energy is not neough to drive them down to zero or to Vin, then the converter works at the boubdary, or in "valley mode".

    But still, the converter works in CCM, therefore the output inductor current never reaches zero. According to the voltage on Vrcs, you can decide where the sync-FETs should be kept off; typically this is done just above the level that the converter enters DCM. If you force this level to zero, the converter never switches the sync-FET off (unless during soft start or protection mode), and it works in CCM mode all the time.

    Best regards,

    Roberto

  • Hi Roberto,

    Sorry for the Typo error. 

    For the 1st query on using PMP8740 for a motor load: Thanks for the input and it will really help us.

    Regarding current sharing: Let me first summarize our goal:

    • We are looking to develop a 5kW PSU unit.
    • Out of the 5kW-3.5 kW is from PMP8740 design and 1.5 kW from LM5170EVM
    • For the 3.5 kW we planned to use 2 units of PMP8740 board in parallel. Similarly, for 1.5kW-2 units of 750W LM5170EVM board in parallel.
    • Will sharing work for this scenario i.e  70-30 ratio.
    • We have procured 2 units of LM5170EVM board and we tried paralleling both. Its working fine.
    • We are also in  process of fabricating the PMP8740 board. Once it its done we will work on sharing (70-30) between PMP8740 and LM5170EVM. Will update you, once it is done. In case if we face problems, we may need your inputs.

    Valley switching: Let  me understand it fully, and will get back back to you. Please try to share any relevant literature's on Valley switching.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    OK, I understood the architecture that you are developing.

    Regarding the explanation about zero voltage switching, like the phase shift full bridge here, please download the follwing application report, which explains in detail this topology.

    Best regards,

    Roberto

  • Hi Roberto,

    Thanks for the document. Will  revert back

    Regards,

    Anbarasan

  • Hi Roberto,

    Hope things are fine... We have assembled the Buck part (DC-DC) of PMP8740 and started testing.

    We made the following the following to test the DC-DC part:

    1) Shorted PWM_Vref P2.4  and PWM_Iref P2.3 both to ground

    2) The delay time setting resistors (R9, R10, R11) are kept same as in the schematic of PMP8740.

    3) Fly back transformer turns ratio is 20:3. We designed it for a output voltage of 48(Nominal). Hence, we changed R19 from 2.37k to 1.5k.

    4) We also changed R34 to 20ohms, R7 to 10k and R69 to 200k.

    5) We added a 100K in parallel to R29, and increased the Vin higher than Vin(nominal)/2 (around 200V).  The converter entered regulation (we observed the waveform across primary side of T4-width of the pulse reduced).  The output voltage was around 32V. We did not apply any load, but the primary side MOSFETs were warmer-without fan and with fan it was fine.

    6)Then, we removed the 100K in parallel to R29 and increased the Vin. Around 305V, the converter entered regulation. The output voltage was around 50V. The load was not connected. The issue is, we are observing a low hissing noise when the converter enters regulation. Is it normal? Do we need to change (increase) the delay time?  Also, Light warm is observed in the primary side MOSFETS -even with fan. Please suggest.

    7) How should we tune tabset? Please help on the procedure.

    8) We used only the rectifier section of PFC board until now. Is it fine or should use the PFC part also for supplying Vin?

    9) Should we load and observe?

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    OK, I agree on all points.

    Regarding the noise when the converter enters regulation, is that due to burst mode? If so, it can depend on the transformer, maybe not glued.

    If it is not glued, nor varnished, you can check if the noise comes from it, by pressing (please use gloves) the core; the noise should stop.

    There is no need to use the PFC stage on, if the voltage on the DC/DC stage is enough for regulation. The difference between PFC on and off, is that when it's off there is a lot of 100 Hz ripple on 400V output, and also the diodes of the PFC will be more stressed because of the high 100 Hz peak current. But this happens of course at medium to high load current.

    Regarding the MOSFET temperatures, it's pretty normal that when ZVS is lost, there is some loss due to the switching (charging and discharging of Coss), but this should not be too high (you can calculate how much loss you have, but you should take into account the primary capacitance of your transformer).

    The Tab set should be fine tuned by watching the voltage on the switch node with a scope; when one MOSFET turns off, at a certain point of load current, you reach valley switching (here the energy stored in the shim inductor is exactly equal to the energy needed to charge/discharge the total switching capacitance (2 x Coss + transformer cap). Then adjust Tab delay so that the next MOSFET is turned on at 1/4 of the resonance, or at the valley.

    Best regards,

    Roberto

  • Hi,

    Today, we loaded the converter up to 4 A. The output voltage was regulated at 50V and the noise also stopped.

    Please help on where exactly to measure , for varying Tab.

    We measured at two points indicated in the Figure attached (vgs and vds). Is it correct?  Should we use two isolation probes for measurement? Do help us out.

    Please try to reply ASAP.

     Regards,

    Anbarasan R

  • Hi Anbarasan,

    That is correct. Please try to fine tune the turn on instant (Vgs) just after the voltage on Vds has reached the valley.

    Regards,

    Roberto

  • Hi Roberto,

    Thanks for your quick response.  

    What exactly do you mean by fine tuning TURN On instant. Should we increase the delay-Tablet?

    Problem is, we need have two isolation probes to measure both of them (Vgs and Vds) instantly. Also, we don't have isolation transformer at the front end-AC grid side.

    Without measuring them, can we randomly increase the delay time, based on observing the temperature of MOSFETS.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    If it is not possible to watch the waveforms in real time, you can optimize the Tab by measuring the temperature of the FET (but this has some delay between the action and the measurement) or better measure in real time the efficiency of the DC/DC stage; I mean, if Vout and load current remain constant, and the input voltage as well, you can fine tune the Tab by minimize the current consumption of the DC/DC stage: this will reduce therefore also the loss on the MOSFETs.

    Regards,

    Roberto 

  • That's great. Thank you.. Will test and let you know tomorrow. 

  • Hi Roberto,

    As per your suggestion , based on the converter efficiency we modified the delay times (tabset and tcdset) to 640ns for left leg-tabset and 570ns for right leg-tcdset. Further increase in delay time, caused the output voltage to drop by 2V i.e from 50V it dropped to 48V. So, we didn't increase further.

    We loaded the converter up to 10A on the 50V side. Its working fine, but the temperature of the left leg MOSFETS is on the higher side, compared with the right leg

    Are we on the right tack. Can we increase the load on the converter? Are the tuned delay times higher which makes body diode conduction interval more?. Please suggest.

    Expecting your feedback.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    The delay times you fine tuned are perfect set up in order to avoid switching losses at light load, and reduce EMI.

    However, as the load increases, the body diode conduction time will be longer, and therefore increasing the conduction losses.

    If this is not a problem for you, you can continue with these delay times, or activate the dependency on the CS signal.

    The slight difference about the temperatures in the left compared to right leg I believe depends on the extra circulating current flowing in the shim inductor, due to the clamping diodes....but also this is normal.

    You may increase the load and watch at the temperatures of the FETs.

    Regards,

    Roberto

  • Hi Roberto,

    Thanks for the suggestions.

    For activating the depending of CS signal (adaptive delay), R8 should be populated and R1 should be removed. Is it fine or anything else has to be changed. Should we again change the original delay or used the tuned delay?

    If Adaptive delay reduce the conduction losses, why R8 is recommended as DNP in the schematic. Are they any drawbacks in adaptive delay approach

  • Hi Anbarasan,

    In my case I didn't use the dependency with CS pin, so, please, follow the datasheet about how to do that.

    Best regards,

    Roberto

  • Hi Roberto,

    Fine. But are any advantages of using a fixed delay approach over adaptive delay? Why did you choose the later?

  • Hi Anbarasan,

    I didn't use the adaptive delay in order to keep the DC/DC stage not too complicated, because the whole project was already complex enough.

    But, of course, there is always room for improvement!

    Regards,

    Roberto

  • Hi Roberto,

    The datasheet says , Adaptive delay  can be generated by connecting the ADEL and ADELEF pins to the CS pin (R8 should be populated and R1 should be removed)-means that it is all left to the controller to change the delay based on the voltage at the CS pin, which looks less complex.

    For choosing the resistor Rab for delay settings, the excel design calculator using the formula shown below:

    But the same, in the data sheet uses a different  one shown below;

    Both looks different. Is it because of the difference that the excel calculator using fixed delay approach and the data sheet specifies the formulae for Adaptive delay.

    Regards,

    Anbarasan R

  • Hi Roberto,

    I understood how those equations work. Will test using the dependency of CS signal and let you know. Thanks for your kind replies.

  • Hi Roberto,

    Loaded the DC-DC board up to 20A today and the left leg MOSFET failed. We tested using the same delay times of 640ns-tabset and 570ns-tbcset. Left leg MOSFET's sink temperature went up to 45deg.C. We did not use the dependency of the CS signal.

    What would the reason for failure. Is it because of the temperature rise-excess body diode conduction?

    Please do revert back.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    If the heat sink temperature reaches 45C there is no problem. Even though, maybe the MOSFET had to dissipate high power for short time, while the heat sink temperature is rising slowly.

    Please replace the failed MOSFET and check again, by increasing slowly the load.

    Starting from light load, please check out the gate-source voltage of all MOSFETs (start with the one that failed) and verify that when the load increases, there is no spike in the gate voltage, which can happen if the gate drive transformer has too high leakage inductance and / or the dV/dT of the switch node is too high. 

    A spike in the gate, at the instant where the second MOFET, of the same leg, turns on, can be dangerous because it creates high shoot-through current, and destroy the FET.

    Best regards,

    Roberto   

  • Hi Roberto,

    Thanks. Please suggest on how to mount the MOSFET to heat sink.  Should we use mica sheet and bolt nut/clip arrangement.

    Will  send you waveform of gate, after replacing the MOSFETS.

    After MOSFET failure, will there be any change in the PCB tracks/capacitance.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    I mounted the MOSFET in my prototype by using Sil-Pad, like the one available on the web:

    Also, please use the isolating washer to avoid that the screw touches the TO220 metal pad:

    This mounting method avoids the need of thermal grease, therefore is more "clean". By the way, you can also use mica sheet + insulating washer and screw.

    Best regards,

    Roberto

  • Hi Roberto,

    Good morning.  We noticed that synchronous rectifier (output side MOSFET) had also failed in addition to the primary side lagging leg switches.

    • Is that the synchronous rectifier failure would have caused primary side switch failure? What could be the reason for secondary side MOSFET failure.
    • We tuned for DCM to CCM mode at 6A and we also observed the Syn.rectifier MOSFET started conducting at 6A, but the failure happened at 20A
    • VDS ((2*Vinmax/turns ratio)*1.5) for syn.recifier MOSFET for our case of 48V is around 190V.  But we are using MOSFET which has VDS of 200V. Should be increase the VDS to accommodate our application of increased voltage.

    Please do reply.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    It is very likely that if there was a fail on a sync-FET, also on primary side one FET can be damaged as well.

    Please, when you repair the prototype and start increasing the load, check continuously what is the peak voltage on both sync-FETs.

    Then select the most appropriate voltage rating.

    Regards,

    Roberto

  • Hi Roberto,

    Noted.

    We repaired and started testing.

    While using R9=52.3k, R10=52.3k our delay times measured at U12 pin 2 and 4 isTabset=610ns and U13 pin 2 and 4 is Tbc=570ns.

    Using the same resistor, why there is delay difference between the two legs(left and right leg)? Is it normal.

    Keeping the duty cycle (Dtyp=0.83% in our case) same, can we set unequal delay settings. Ex. Tabset=app. 980ns and Tcbset=app. 200ns. If we do so, the output voltage drops. Why does it happen? Please do explain...

  • Hi Anbarasan,

    I suppose you are using the UCC28951, isn't it?

    Please check out the tolerances on the datasheet about these delay times: they are, worst case, +/- 20%.

    Regards,

    Roberto

  • Hi Roberto,

    Ya, we are using UCC288951. If is it normal, then fine.

    Keeping the duty cycle (Dtyp=0.83% in our case) same, can we set unequal delay settings. Ex. Tabset=app. 980ns and Tcbset=app. 200ns. If we do so, the output voltage drops. Why does it happen? Please do explain...

  • Hi Anbarasan,

    The output voltage drops only if you reached the maximum duty cycle, then the converter is not anymore able to stabilize the output.

    If this is the case, you have several possibilities to avoid it:

    1) Decrease the delay Tba, since 980nsec looks a bit too high

    2) Decrease the value of the shim inductor, because this inductor also reduces the equivalent duty cycle of the phase shift full bridge

    3) Increase the minimum input voltage

    4) Change the transformer turns ratio with a lower value

    Best regards,

    Roberto

  • Hi Roberto,

    On the PMP8740 (Phase shifted Buck Converter), we increased the load up to 28A and its working fine.. We planned to increase if further up to 35A. Hope it works.

    Need your help on LM5170-Q1 Bi-directional demo board. We want use the analog voltage outer loop control in BUCK mode and ISETD in BOOST mode i.e CC mode in boost operation and CV mode in BUCK operation.  Please suggest on the same.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    OK for the PMP8740, please check out the maximum voltages on synchronous rectification FET as soon as you increase the load.

    Regarding the LM5170, I a not an expert of this controller. Can you please open another thread about it; this way other colleagues will give you more detailed information.

    Best regards,

    Roberto

  • Hi Roberto,

    How are you? Hope you are doing good.

    We increased the load up to 35A. The voltage across the syn.FET is attached. The output voltage drops to 46V (Nominal is 48V). What could be the decrease for the drop. Please suggest.

    Also, we need to parallel two PMP8740 boards (increasing power  up to 3.5kW) using the SYNC pin. Please guide us on the same.

    Expecting your response.

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    Sorry for the late reply, but I am on vacation until the 28th of August, so there will be some delay during my answers.

    The waveform of the sync-FET looks good and there is nothing wrong in that. I believe you are working with high value of duty cycle, therefore the controller is not able anymore to regulate the output voltage. As written in my last reply, you might want to increase the voltage on the PFC boost, from 390V to 400 or 405V (if you still have margin) or decrease the number of turns on primary side of the transformer. One or two turns less should increase the peak voltage on the secondary side a bit, please check at the same time the sync-FET voltage. Another way is to decrease the value of the shim inductor, since this component is also reducing the net maximum duty cycle.

    Regarding the synchronization of two units, you need to set one converter as master and the second one as slave, and follow the indications in the datasheet under the section 7.3.15; I copied and paste it below FYI.

    Best regards,

    Roberto

  • Hi Roberto,

    Thanks for your suggestions on voltage drop. We will work on it.

    Regarding syn, we have gone through the section 7.3.15.  Our major query in it is-Should we use the voltage and current loop of the slave controller? i.e Should we do any modifications to the EA+ and EA- pin of the slave controller?

    Regards,

    Anbarasan R

  • Hi Anbarasan,

    You can put two DC/DC converters in parallel in two main ways.
    1) The way I made in the PMP8740, where two completely separated modules (each comprised of PFC + DC/DC and microcontroller) communicate digitally by means of serial communication, and share the information about the output current. In this case, you should have plenty of documentation about this way.

    2) You can use a single microcontroller, and put two controllers UCC28951 on the same board, controlling two separated DC/DC power stages. This way you can have a single voltage loop and a single current loop. In the datasheet it's explained how to connect them together in  master-slave architecture. If you have a single module, with single housing, interconnecting all power stages together (and therefore not going outside the enclosure), I suggest to follow this second method, and therefore follow the datasheet of UCC28951.

    Best regards,

    Roberto