• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 40 subscribers
  • Views 232 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIDA-01064: Help understanding GND connection between Power MOSFETS in reference design

Samuel Anderson
Prodigy 10 points
Part Number: TIDA-01064
Other Parts Discussed in Thread: TIDA-00751

I need help with a basic understanding of why there is a ground connection between the power MOSFETS in TIDA-00751, and TIDA-01064. 

It seems to me that when the MOSFETs are conducting, that there will be a short directly to the ground between the two MOSFETs. I'm sure this is not the case, but I can't seem to figure out why it does not immediately short to ground.

Thanks,

Sam

  • 0
    TI__Mastermind 29525 points

    Hi Sam,

    Thanks for the inquiry. I was not directly involved in either of these reference designs. I'll look into this further and get back to you when I have more information.

  • 0 in reply to John Wallace1
    TI__Mastermind 29525 points

    Hi Sam,

    For TIDA-01064, the circuit is a totem pole bridgeless PFC configuration and the power FETs are switched as described in section 1.2 of the document in the link below. This switching scheme avoids any shoot thru or shorting to ground. In TIDA-00751 (isolated, SPST solid state relay), the FETs are in a back-to-back, common source configuration and are switched on and off at the same time. Their gate terminals are tied together as are their source terminals which means that VGS is the same for both devices. The common source terminal is not tied to GND. The back-to-back configuration means there will be no current flow thru the body diode of either FET when they are turned off. When the FETs are on, current flows thru both devices to the load which is connected across the J5 terminal block on the board.