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Part Number: TIDA-00901
I have a question on the MOSFET selection for the reverse battery protection in TIDA-00901 design reference. Vishay SQJ422EP-T1-GE3 was selected for 20-A application. During the normal operation (no reverse voltage), the MOSFET is believed to be operating at DC region. The SOA chart below shows that the maximum allowable current I_D should be less than 5-A at 12-V V_DS. Thus, the MOSFET is not safe to be operated in the case. I am wondering whether there is anything wrong in my understanding.
Thanks for the inquiry. I am the applications engineer for TI's power MOSFETs. I didn't working on this reference design but have reviewed the schematic. During normal operation, VCPH should be pulled up sufficiently above the input voltage to turn on and fully enhance Q8. Under those conditions, the drain-source voltage, VDS, is approximately 0V. We're most concerned about SOA during the turn-on and turn-off transitions of the FET as it passes thru the saturation region (Vds > Vgs - Vth) from cutoff to the linear region (Vds << Vgs - Vth) and vice versa. During these transitions there is both voltage (Vds) and current (Ids) which is a high power dissipation condition. When the FET is fully enhanced, we're most concerned about the conduction loss (I^2 x Ron) and the ability to remove the heat from the package. During cutoff, we want to make sure Vds < BVDSS of the device. In order to determine if the FET is operating within the SOA, we need to know the switching transition times during turn on and turn off. Please refer to the blog in the link below for more information on SOA.
MOSFET technical information on ti.com here
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In reply to John Wallace1:
Thank you very much for your quick reply. Your answer is very helpful.
I have a further question regarding the MOSFET selection. The selected MOSFET SQJ422EP-T1-GE3 has 3.4 mohms R_DS(ON) at 25C. When the junction temperature at 150C, the R_DS(ON) will be 1.9x higher to reach 6.5 mOhms. Thus, the heat generated from Q8 at 20A current will be at least 2.6W. The datasheet says that the thermal resistance from the junction to ambient of the package is 65K/W. If a 4-layer board with large copper area is designed, the best thermal resistance of the package could be 35K/W. The junction temperature could be over 90 degree C higher than the ambient temperature. Thus, it could not be used for the automotive application with ambient temperature over 80 degree C. Could you please comment whether my understanding is correct?
Thanks and have a nice weekend,
In reply to John Pan:
Thanks again for your interest in TI FETs. I believe your understanding is correct. Please visit our MOSFET Support & Training page at the link in my signature. There you will find a blog series on understanding MOSFET datasheets including one on thermal impedance (link below). FET vendors can only guarantee the junction-to-case thermal impedance as that is the only thing we can control. The junction-to-ambient depends on PCB layout and stackup. With a good layout with multiple layers, I've seen effective junction-to-ambient ambient thermal impedance in the range of 20C/W to 25C/W. Please note, TI does not make any automotive qualified FETs.
Thank you. I enjoyed reading your technical articles.
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