I am trying to design a dc dc converter(Vin:50dc, Vout:12,8A) using LM5119 interleaved operation, and whenever i short Comp1 with Comp2 as per directions in the datasheet i get this,
"ERROR(ORPSIM-15143): Voltage source and/or inductor loop involving X_U1.E2. You may break the loop by adding a series resistance"
and if i design their separate compensator networks or if i add a series Resistance between Comp1 and Comp2, i get convergence problems.
Both channels work fine independently, (I simulated the design that was provided along the model).
this is the pspice netlist
** Creating circuit file "Simulation2.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
.LIB "G:/snvm383/LM5119_PSPICE_TRANS/LM5119_TRANS.LIB"
* From [PSPICE NETLIST] section of C:\Cadence\SPB_16.5\tools\PSpice\PSpice.ini file:
.lib "nom.lib"
*Analysis directives:
.TRAN 0 1000ns 0 1ns
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC2.net"
**** INCLUDING SCHEMATIC2.net ****
* source TRY-11
R_RT 0 N99286 17k TC=0,0
C_Chb2 N99104 N99272 470n TC=0,0
C_Chb1 N98834 N99394 470n TC=0,0
R_Rfb2 N98798 N98962 14k TC=0,0
R_R23 N98652 N98522 2m TC=0,0
R_Rramp2 N99390 N99104 500k TC=0,0
C_Css1 N99734 0 50n IC=0 TC=0,0
C_C2 N98652 0 5u IC=36 TC=0,0
R_R22 N98546 N98522 2m TC=0,0
C_C1 N98546 0 5u IC=36 TC=0,0
C_Css2 N98924 0 50n IC=0 TC=0,0
C_C5 N98484 0 5u IC=36 TC=0,0
R_Rramp1 N98850 N98834 500k TC=0,0
R_Ruv1 0 N98888 7.04k TC=0,0
C_Cvcc1 0 N99340 1u TC=0,0
C_Cramp1 0 N98850 213p TC=0,0
C_Cvcc2 0 N99248 1u TC=0,0
D_D1 N99340 N99394 PMEG6010
X_U1 N98522 N98888 N98798 N98820 N98850 N99734 N99286 N99834 N104274 0
+ M_UN0001 N99390 N98924 N98820 N99248 0 0 N99508 N99496 N100070 N99768 N99104
+ N99272 0 N99248 N99164 N99404 N99622 N99098 N98834 N99394 N99340 LM5119_TRANS
R_R21 N98522 N98466 100m TC=0,0
X_M5 N98522 N99098 N98834 IRFP064N
X_M6 N98834 N99622 N99404 IRFP064N
C_Cramp2 0 N99390 213p TC=0,0
R_R26 N98484 N98522 2m TC=0,0
R_Rs1 N99164 N99404 15m TC=0,0
V_Vin N98466 0 50Vdc
R_Ruv2 N98522 N98888 100k TC=0,0
X_M7 N98522 N99768 N99104 IRFP064N
C_Ccomp N98798 N100486 589n TC=0,0
C_Chf N98798 N98820 313p TC=0,0
R_Rfb1 0 N98798 1k TC=0,0
R_R25 N98752 N98522 2m TC=0,0
C_Cres N99834 0 0.47u TC=0,0
R_Rs2 N99508 N99496 15m TC=0,0
C_C4 N98752 0 5u IC=36 TC=0,0
R_R24 N98702 N98522 2m TC=0,0
R_Rcomp N98820 N100486 90k TC=0,0
D_D2 N99248 N99272 PMEG6010
C_C3 N98702 0 5u IC=36 TC=0,0
X_M8 N99104 N100070 N99496 IRFP064N
X_L1 N98834 N98962 LDCR PARAMS: L=47u DCR=20m IC=0
X_L2 N99104 N98962 LDCR PARAMS: L=47u DCR=20m IC=0
R_R29 N109368 N98962 5m TC=0,0
R_R28 N1094561 N98962 20m, TC=0,0
R_R33 N109368 N98962 3m TC=0,0
C_C23 N109368 0 45u TC=0,0
C_C22 N1094561 0 470u TC=0,0
**** RESUMING Simulation2.cir ****
.END
ERROR(ORPSIM-15143): Voltage source and/or inductor loop involving X_U1.E2. You may break the loop by adding a series resistance
I want to know that
a) Adding a small resistance between Comp1 and Comp2 will affect the output?
b) Can i use both channels independently and short their outputs?
c) Can the series resistance between comp1 and comp2 can cause convergence problems?
d) Does anyone else has the same problem?
e) Is it A design flaw, or a model flaw?
A Quick reply would be awesome, i am already behind my schedule, Thanks.
