PSPICE-FOR-TI: Last daisy chained SMPS won't come up, and both have wrong voltages.

I'm also unsure why the PG pin on the VCCO_HP_3V3 instance of the uPOL sheet has an undefined float property error when it has a 100k pullup on the uPOL child sheet, and a 1G pullup on the main parent sheet. Could this have something to do with my issue?
The 1G resistor didn't stop PSPICE from complaining about floating nets, like my red note indicates.

I've already tried restarting PSPICE which seems to resolve other issues I've seen. But not this one.

Hi Dan,

Please do share the project with us. Find instructions for sharing here: https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/969692/faq-pspice-for-ti-how-do-i-share-pspice-for-ti-projects?tisearch=e2e-sitesearch&keymatch=faq%252525253Atrue

I will look into the problem you have described.

Thank you,

Jackie

Thanks Jackie,

That would be very much appreciated.

Please see attached.

PSpiceAchive_Daise_Chain.zip

Kind regards,

Dan

Hi Dan,

Thank you for sharing. I will let you know my findings.

-Jackie

Hi Dan,

I observe what you are describing, but I do not have a solution for you yet. I am working with the product line to dig deeper into the problem. 

Thank you,

Jackie

Thanks Jackie,

Have you had any luck?

Kind regards,

Dan

Hi Dan,

We're still looking at this. There is definitely something odd here, but we haven't found the cause yet. I will let you know when I find more. 

Thank you,

Jackie

Hi Dan,

Can you try changing the Steady_state parameter in the IC from 1 to 0?  This is causing the IC to try and start in steady state and not ramp up with SS as would be expected.

Thanks,

Chris

Thanks Chris,

With steady_state set to 1, the 1V8 supply produces 1.93V, but with steady_state set to 0, it produces 152mV.

I tried increasing the simulation time from 100µs to 1ms, still with steady_state at 0, but that just produces the attached error.

I'm using the Main-test simulation profile because I haven't figured out how to delete main-SteadyState or change the sheet in the hierarchy that it uses.

main-SteadyState was created before I changed to a hierarchical structure.

Kind regards,

Dan

Hi Dan,

With your 22nF SS/TR cap, Vout should take at least 5 msec to ramp up to the full voltage.  So, the simulation time should be at least that long, or you can reduce the cap value.

Let me try and loop in someone to comment on your error.

Chris

Hi Dan,

As Chris has mentioned, the soft start time of each of your SMPS would be 5ms. Please use the simulation time of 12ms as you're chaining two devices.

Also, with regards to the error you're facing, it looks like PSPICE is unable to converge. Please go to PSPICE--> Edit Simulation profile and edit the following parameters.

Maximum Step size = 50ns, ABSTOL = 1n, ITL2=40, ITL4=60. I believe this should solve it.

If you're still facing issues. Please archive the project and share it back with us so that we can have a look. Thanks.

Regards,

Karthik