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TIDA-010031: Configuring OPAmp output and ADC input on the same pin

Nikhil V
Prodigy 10 points
Part Number: TIDA-010031
Other Parts Discussed in Thread: DRV8320

Hi All,

For the TIDA-010031 board I am configuring pin 1.2 as -ve, pin 1.3 as +ve inputs of the opamp & pin 1.1 as output of the Op-Amp. Same pin 1.1 is configured as the input of the ADC. At pin 1.1 I see less voltage then anticipated. Following is how it is connected.

IS_IN+ and IS_IN- are input to the SAC0 and IS_O is the ouput. Same IS_O is the configured as input of the ADC A1. After configuration I see voltage on node IS_IN+ as 1.38V instead of 1.5V.

pin config

// Configure ADC A1 pin
P1SEL0 |= BIT1;
P1SEL1 |= BIT1;

P1SEL0 |= BIT1 + BIT2 + BIT3; // Select P1.1 P1.2 P1.3 OA function
P1SEL1 |= BIT1 + BIT2 + BIT3; // Select P1.1 P1.2 P1.3 OA function

Configuring SAC

SAC0OA = SACEN | OAEN | NMUXEN | NSEL_0 | PMUXEN | PSEL_0;
SAC0PGA = MSEL_2; // non-inverting mode */

Configuring ADC

ADCCTL0 |= ADCSHT_1 | ADCON; // ADCON, S&H=16 ADC clks
ADCCTL1 |= ADCSHP; // ADCCLK = MODOSC; sampling timer
ADCCTL2 &= ~ADCRES; // clear ADCRES in ADCCTL
ADCCTL2 |= ADCRES_2; // 12-bit conversion results
ADCMCTL0 |= ADCINCH_1; // A1 ADC input select; Vref=AVCC
ADCIE |= 0x00; // Enable ADC conv complete interrupt

P1SEL0 |= BIT1 + BIT2 + BIT3; // Select P1.1 P1.2 P1.3 OA function
P1SEL1 |= BIT1 + BIT2 + BIT3; // Select P1.1 P1.2 P1.3 OA function

  • 0
    TI__Intellectual 2105 points

    Hi,

    Is the situation you are testing without a motor? If drv8320 is not started, is_in+ has a 1.65v bias,

    Thanks

    Jenson

  • 0 in reply to Jenson
    Prodigy 10 points

    Hi Jenson,

    Yes I am testing without a motor. IS_IN+ should have a bias of 1.65V when the drv8320 is not started, but when I configure the SAC as non inverting mode with gain 1, the output of SAC IS_O pin, I see voltage as 1.38V instead of 1.65V.

    It there internally any series resistance with the input of the OPAmps ?

  • 0 in reply to Nikhil V
    TI__Intellectual 2105 points

    Hi,

    Please test after DRV8320 ENABLE. After DRV8230 is ENABLE, IS is connected to the internal op amplifier of DRV8320, and there will be no voltage division. Similarly, the op amp in the MSP430 will also not have voltage division.

    In addition, please make sure that the 3.3V power supply and the resistor you choose are correct.

    Thanks

    Jenson

  • 0 in reply to Jenson
    Prodigy 10 points

    SAC is internal to MSP430, an IS_IN+ node as shown in the schematic above is an input to SAC. This node IS_IN+ has the voltage of 0.34 instead of 1.65(which we should get through voltage divider). Now with the R31 and R30 the gain is 4, hence output of SAC module is ~1.36V. But my question is when I configure SAC + ADC I dont see voltage of 1.65V at IS_IN+, instead I see 0.34V?

  • 0 in reply to Nikhil V
    TI__Intellectual 2105 points

    Hi,

    Understood,you mean you IS_IN+ is 0.34V,and don't know why, right?

    So I would like to know,how you measure this 0.34V? and if the 3.3 bias voltage is normal ? and if you are enable the DRV8320? and has the 430 program been burned?

    Thanks

    Jenson

  • 0 in reply to Jenson
    Prodigy 10 points

    Thank you Jenson,

    I am measuring 0.34V on multimeter at node IS_IN+ wrt ground. 3V3 node is 3.3V.

    If I enable the drive, IS node which is current sense output based on the output current is added along with the offset to IS_IN+ node

    Yes MSP430 has running code in it and the configuration of SAC and ADC is mentioned in the question.

    Let me know if you want me check anything else?

    Regards,

    Nikhil

  • 0 in reply to Nikhil V
    TI__Intellectual 2105 points

    Hi Nikhil,

    Pls use the code from our TIDA-010031. There is a configuration error in your code

    // Configure ADC A1 pin
    P1SEL0 |= BIT1;
    P1SEL1 |= BIT1;

    P1SEL0 |= BIT1 + BIT2 + BIT3; // Select P1.1 P1.2 P1.3 OA function

    Pls check below configuration

    /* ADC Input Channels Selected as ADC function eliminates parasitic currents flow */
    P1SEL0 |= BIT0 /*| BIT1*/| BIT4 | BIT5 | BIT6 | BIT7;
    P1SEL1 |= BIT0 /*| BIT1*/| BIT4 | BIT5 | BIT6 | BIT7;

    Thanks

    Jenson