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UCD3138: Understanding the TIDA-00653 circuits

Part Number: TIDA-00653
Other Parts Discussed in Thread: UCD3138

Hi guys,

I’ve got a couple of questions for you regarding the TIDA-00653.  I’m having a hard time understanding what the current loop of the firmware really controls.


My understanding of the circuit is the following:

When the load from one side diminishes, automatically the other voltage is going to become the source.
Let’s say for example there is a high current demand on the 48V. The 12V will then become the generator and the DC/DC will change direction. Once the 12V is the generator, the current seen by the sense logic will be reversed. The MCU will then see this switch and switch its logic.


The part I’m not sure to understand is the following:

If the analog circuits have already electrically made the switch from one side of the converter to the other, what does the logic of the MCU really drive?

Furthermore, I’m going through the code and I can’t figure out which electrical changes will me made once the MCU changes its state in its state machine. What will physically change on the board?


Also, do the PWMs change (any change in frequency/duty cycle) when the converter goes from one direction to the other, or do they always stay the same ?


Ultimately, I’m wondering I don’t see any controller (PI/PID). Who assumes the role of slowly ramping up the voltage of the converter? Is it the UCC2721XDRM circuit that charges the gate?


Thanks a lot for the support, you guys do an amazing job.

  • I suggest reading the User Guide that comes with the code, and then looking through the code.   I'd also suggest going through the UCD datasheet. 

    If you are planning to write firmware yourself, you should also check out the UCD3138 Technical Reference Manual

    Filter 0 is a hardware PID filter on the UCD which is used to provide the pulse width to the UCD.

    The Current handler firmware helps decide whether the program is in Buck, Boost, or Standby mode by monitoring the current flow amount and direction.  

    Then there is a sequence of modes and another state machine that helps with the process of switching.  They are different for Buck and Boost and seem to be in Buck.c and Boost.c.  

    Here is the dispatch code for the different states in buck mode.

    switch (buck_state)
    case ENTRY:
    case WAIT_TO_SETTLE:
    case PRE_BIAS:
    case RAMP:
    case SYNC_FET_RAMP_UP:
    case RESPONCE_TEST://Used only for PID tuning.
    // responce_test();
    case STEADY_STATE:

    You can see that the MCU is doing quite a lot of work here.  

  • You have rejected this answer, but you have not spelled out how it is unacceptable.  I'll give you some more detail to help you see what the MCU does when the mode switches.  There are no changes in the electrical connections on the board, only changes in how the code manages them.  

    I can't describe all of the changes that take place through all the states, so walk you through the entry states for buck and boost.

    You can find the code to do this in the handle_entry_state functions in buck.c and boost.c

    First both of them clear filter 0.  As I mentioned, filter 0 controls the duty cycle.  Clearing it means that the DPWMs will start out with a duty cycle of zero.

    Next the DPWM pins are configured using the intra mux.  In the boost stat, the intramuxes are configured with 0s, which means that the duty cycle D will appear on DPWMA, and the delayed N-D will appear on DPWMB.  For the buck state, 3s are put into the intramux, which will make D appear on DPWMB, and N-D will appear on DPWMA.  

    Next the DPWMs are configured for the appropriate dead times for buck or boost.  

    Next the sample trigger is configured.  This signal comes from the DPWM and goes to the front end of the hardware PID filter to start an EADC conversion.  The result of the conversion is used as an error signal to the filter, which will cause the filter output to adjust the pulse width to reduce the error.

    After that, the EADC_INV bit is configured for the buck or boost mode.  In buck mode, the EADC is not inverted, in boost it is.  This is used to reverse the sign on the error, as the current is reversing.  So in buck and boost the relationship between the error and the duty cycle is inverted, so the EADC data is inverted to make sure the filter has negative feedback in either direction. 

    Those are the major changes in configuration, but at the end of the handle entry state, you will notice that the state goes to wait_to_settle.  More configuration changes and monitoring are made until it goes to a steady state.  And, of course, it can go back to standby, and then go back to buck or boost mode. 

    If you want all the details, you will need to look through the documentation that I mentioned and look through the code, starting with the state machine I showed you before and going to each state in turn.  

    I won't mark this as resolved.  If it's not resolved, please tell us what else you need to have explained.

  • It's been quite a while, so I'll assume this is resolved.