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PMP10352: Knowing about the parameters

Part Number: PMP10352
Other Parts Discussed in Thread: CSD18504Q5A

Hi,

I am Guillermo Durà, from Magnetika.

We are trying to create our own transformers with litz wire and E cores. At this point, as a first prototype, we are using your PMP10352 isolated flyback converter as a reference.

Therefore, we are connecting in the right pads, the terminals of the transformers. We are doing just one with two windings at this moments since it is easier.

In simulation, we see that whenever there is some leakage in the transformer, there is a lot of ringing in the VDS signal for the FET, and the one used in the reference design is rated to be 40 VDS, so therefore, I think that it will probably be burnt. So I have a pair of questions regarding this reference design.

Did you have any leakage inductance in the actual transformer from PULSE used? How much is it?

In practice, did you obtain a lot of ringing in the currents and the voltages through the FET?

  • Hi Guillermo,

    The transformer has a 1:4 step up turns ratio from primary to secondary.  The nominal inductance at 0A is 10uH.  The maximum leakage is specified as 0.18uH (1.8%).  1-2% leakage is typical for this type of transformer.  The actual leakage is probably less than this, but I did not measure it.

    I have attached the drain to PWRGND waveform of the FET with a 12V input and 360mA load.  The peak voltage is less than 30V.

    D1/R1/C4 is an RCD clamp that limits the initial turn-off voltage spike.  The voltage ringing after the initial voltage spike can be damped with an R/C snubber from drain to PWRGND, but this design did not include one.

    The leading edge of the FET current waveform will have a voltage spike from the gate drive current pulse that goes through the current sense resistor R8.  R6/C13 will filter this voltage spike.

    Thanks,

    David

  • Hi David,

    Thank you for the fast repply. 

    Now, I am trying to simulate in LTSpice the values you told me. So based on that, I create the following model for the transformer you used for the flyback reference design. The coupling value is based on the leakage inductance you specified me,  and the secondary inductances are based on the turns ratio and the datasheet from PULSE electronics. 

    The entire schematic includes all the components used from the schematic provided in the reference design PMP10352 but the transistor used is the BSC050N04LS since I do not have its SPICE model. Nevertheless, that transistor matches the specifications from the CSD18504Q5A used.

    My question then is, how would you suggest to model the transformer in LTSpice? Because the waveforms, shows a lot of ringing.

    Thanks in advance,

    Guillermo

  • Hi Guillermo,

    Unfortunately we are not experts on modeling or LT Spice, so it is difficult for us to help you with your simulation.

    In general the approach you have take above seems to be in the right direction, I am thinking that maybe you are missing some resistance in the model that would help to damp the ringing. 

    Sorry to not have more help for you.

    Thanks,

    Robert