I read the design guide and the working idea is clear to me; there is a dual channel with self test and single fault resistance; that should qualify for SIL3/PLd. However I don't have really worked with SILs but only with PLs, so there's a thing I don't get.
How could be it rated SIL3/PLd if the testing path and software is only SIL1 (the external MCU, suggested as a C2000 part). The MCU is substantially a category 1 system with 60% diagnostic coverage (due to self tests); if it's used in the control path of a category 3 subsystem (the STO function). Would that impair the whole subsystem level?
Or, alternatively, the explanation is: a fault in one of the working channel is always detected by the monitor (and the safe function is ensured by the other channel and/or forcing pulses) while a fault in the monitor goes undetected (acceptable as category 3 but not as category 4) but safety is ensured by the working channels (since only a single fault is assumed they are both considered as working correctly).
Have I missed something?