Tool/software:
I was exploring the control loop of CLLLC, and I have a few queries. Please help me with clarification.
1. On the secondary side of CLLLC, there is one block named Simple SR-Driver connected between the drain and source of each secondary side mosfet. Inside that block, what is the logic for VSD_ON, IOFF reference? Why have its values 1V and 5A been taken as references?
2. In the IOFF comparator, IOFF is connected at a non-inverting pin of the comparator. So the output should be logic low for greater than 5A of sense current, but in simplis it is behaving differently.
Please find the attached screenshot.