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LM5146-Q1: LM5146Q1 Output voltage is dipping when loaded

Kranthi Reddy
Prodigy 10 points
Part Number: LM5146-Q1
Other Parts Discussed in Thread: LM5146,

Tool/software:

Hello team,

I'm Using LM5146Q1 in one of my applications. Input ranges from 35V to 54V, Output is 12V, 10A. I have designed the converter and during no load im getting the output voltage as 12. When I started loading the minimum load (around 50mA) also the output voltage is dipping to 5~6V.  I'm using MOSFET Rds(11mOhms) on for the current sensing purpose & Rlimit=634 Ohms. Could you please help me on this.

Regards,

Kumar

  • 0
    TI__Guru 68757 points

    Hi Kumar,

    Please send the schematic and a completed quickstart file, so I can review the design. Note the specs are are quite similar to that of the LM5146 EVM, which is setup for 12V/8A/400kHz.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Timothy,

    PFA of the schematic. Not finding the option to attach the excel. I have shared the snapshots of quick start calculator. Diode ( D1) is not populated

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    The 2 x 22uF output caps will probably be only 8uF each at 12VDC. Please verify and update the Cout value accordingly, as this affects compensation component calculations (50uF seems too high).

    You can drag the quickstart file into the chat window to attach it.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Timothy,

    Could you please elaborate the below line.

    The 2 x 22uF output caps will probably be only 8uF each at 12VDC.

    In the evaluation board of TI the output capacitance used is much higher (5*22uF)

    LM5146-Q1 Quickstart Tool r2 - 48Vin 12Vout 10A 400kHz.xlsm

    Regards,

    Kranthi

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kranthi,

    The effective capacitance of ceramic capacitors decreases with applied voltage. A 22uF/25V cap at 12V is approximately 8uF. Use the simsurfer tool from Murata to check.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    HI Timothy ,

    I have checked by reducing the capacitance. Still facing the same issue. Is there any other modifications has to be done in the schematics? 

    Also I observed that whenever I'm loading the Vcc voltage has been falling from 7.49 to 7.08V & PGOOD is falling from 7.47 V to 0.007V? 

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    The VCC voltage should be at 7.5V right up to the VCC current limit. Try measuring the current into the VIN pin of the IC (measure voltage on the series resistor).

    Also, when you reduce the output cap to the correct value, the loop crossover likely exceeds 15-20% of Fsw, making the loop unstable.

    I recommend trying your circuit on the LM5146 EVM, as it is setup very similarly. Does your layout match the EVM closely? Send it on for review.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Timothy,

    I understand that system may go unstable due to output capacitance. But even for 10mA load also the output voltage is dropping. 

    Across the R2 (Vin) the voltage is 0.006V in no load and the 0.013V in the loaded condition.   

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    There should be a solid GND plane on layer 2, close to the top layer. SW should be minimal area, no vias and no internal layer copper. See the layout guidelines in the data sheet and refer to the EVM layout.

    Also, what is L3 here? A second inductor may result in instability as well. Is the FB voltage regulating at 0.8V?

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    TI__Guru 68757 points

    Also, for the layout - it is critical that the ceramic input caps are across the FETs. See app note SNVA803 for more detail.

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Timothy,

    I have provided the GND plane at the layer 2 . As I have only 2 layers wherever possible i have provided the GNF plane. C4,C20 (around 10uF) are nearer to the Q1. SW area also tried to keep as small as possible.

    The extra inductor is the Pi filter placed at the output of the converter. FB voltage also falling w.r.t. output voltage.

    Reards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    An output post filter makes stability very difficult and is not modeled in the quickstart. You shouldn't need it, so consider removing L3.

    Also, note the GND plane on layer 2 should be unbroken under the FETs, input caps and controller. The input caps should be super close to the FETs, and the gate loops should be tight (with HO routed beside SW).

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello,

    This L3 I have already removed and the issue is same with little higher voltage when loaded( earlier dipping to 5.5V and now its in 7 to 8V range). I have removed the snubber circuit.  As I have two layers and In 2nd layer below the FETs VIN plane and SW plane is added through Vias for better heat dissipation and other places implemented the GND plane.  SYNCIN is shorted to gnd and SYNCOUT left floating. Increased the VCC cap to 4.4uF.

    The VCC is ramping down to UVLO and parallelly my gate voltages are falling to zero. Whenever there is switching happening the Vcc is oscillating and slowly falling to zero and coming back to high ... the same is repeating..  Checked with gate resistor of 10, 5,2.2 Ohms... Still no improvement. Do you have any suggestions to get  make the Vcc constant? This is at no load after making above changes.

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    Prodigy 10 points

    Hello,

    We have found that the diode emulation mode is not working properly. The bottom switch is turning on more time at  loading (light load conditions) which is making the inductor current negative and affecting the control. We have removed the LO gate resistor and started to operate with the body diode of MOSFET. Now we are getting the stable 12 volt output after loading also. But what we have observed is the Vcc is not stable at 7.5V. When we are loading it it is reduced from 7.5V.  Till 1A we loaded. Vcc is different for different loads. 0.1A Vcc is 7.5, 0.2A Vcc is 7V, 0.3 A Vcc is 6.8, o.4 Vcc is 6.4V, 0.5 Vcc is 5.8V, 0.6A Vcc is 5.4V, 0.9A Vcc is 6.2V, 1A Vcc is 6.6V...Is thee any way to get the stable 7.5V from VCC?

    What might be the reason for failing of diode emulation mode? We have shorted SYNCIN pin to AGND as recommended. 


    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    How is the SW trace routed back to the controller? Diode emulation mode measures the SW node voltage to detect the current changing polarity.

    Regards,

    Tim 

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello,

    SW is rooted in the 2nd layer as below.

    Also any idea why Vcc is changing w.r.t. load?

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    VCC should not change with load, unless it is being overloaded. Is the VCC cap close to the VCC and PGND pins of the IC? We normally use at least a 4-layer board with controllers – this allows a full GND plane on layer 2, which is really helpful.

    Regards,

    Tim

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Just looking at the top layer, there is a big GND return loop. Try adding a VCC cap across the pins. Note also that PGND and AGND pins should tie to the DAP area under the IC (see the EVM layout for that detail).

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    After increasing the Vcc capacitor to 4.4uF, there is no improvement. We have tried the below two ways and in both the Vcc is maintaining the voltage above 7.2V.

    1) Bootstrap resistance increased to 10Ohms. VCC is maintained constant

    2) Connected the bootstrap to VCC through the external diode. Vcc is maintained constant

    Internal bootstrap diode drop is very high.

    Also we need to check the below points.

    When we connected the SYNCIN pin to GND( enabling the diode emulation mode). In this instance the bottom switch gate is operating at fixed frequency and it is not increasing when we increase the load. Vsw is changing w.r.t. load and it is moving from DCM to CCM as expected.. For certain period the bottom switch is operating and after that the body diode is conducting.  I assume there is a fault ZCD detection at Vsw and stopping the PWM pulses to bottom switch. What might be the reason for the constant PWM at the bottom switch? Is there any way to delay the ZCD triggering( in case if it is triggering for false ZCD)?

    Regards,

    Kranthi

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kranthi, I will study this and get back to you shortly.

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    Is there any update on the above query?

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kranthi,

    The SW node voltage waveforms looks okay, but the low-side FET gate voltage waveform look very noisy.

    Looking at the layout again, I don't see the pad for the gate pin of the low-side FET Q2. It looks like GND is running all the way through here.

    PS: no need for antiparallel diode D1 across the low-side FET.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    TI__Guru 68757 points

    By the way, when SYNCIN is pulled high (to VCC) to force FPWM, does the low-side gate drive look okay? Send on that waveform as well.

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    As of now D1 is not populated. Gate of Q2 is connected in top layer.

    Regards,

    Kumar

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hi Tim,

    The low side gate is continuously ON when the top side switch is OFF and it is constant from no load to full load.  

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    So everything is fine is FPWM?

    Note there should be GND plane directly under the gate trace (as this is where the return current will flow). I see the GND is cut up, complicating the return and increasing gate loop parastic inductance - this explains why the low-side gate wavefrom is ringing so much.

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    1) Yes its working with FPWM. But if we are loading more the output voltage is falling? The compensation circuit is not working as intended. We have placed the compensation values as per the Quick start calculator. But the output is falling abruptly with little load also and voltage is fluctuating. . Do you have any suggestions on this to make the stable output voltage? Also the output voltage is reducing when we increase the load. Looks like the FB circuit and comepensation is not working properly?  The quick start calculator compensation values are not helping to stable the circuit.

    2) My top switch is heating for light loads also. Around 4A it is going to 115C which is completely unacceptable. My switch is IAUC60N10S5L110. I assume the switching losses are more.

    3) When my board is connected in the system  , due to high inrush currents requirements of other modules ,the output voltage of my board is falling to zero and turning of my board. After the initial transients the board is not coming back to normal operation. Is there any way to prevent the in rush current other than the soft start? Also after the transients the board has to work as expected but its not happening.

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    It may not be compensation. Is the switch node voltage stable? Can you power an electronic load without any issues?

    Also, is the inrush current from the downstream modules high enough to trigger current limit of the LM5146-Q1 design? I recommend modifying the EVM as needed and use that to power your system.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    I can able to power on the electronic load without any issue, The below image I have loaded 4Amps constantly. My SYNCIN pin is floating .

    Yellow is Vds of top switch, Blue is Vds of bottom switch, red is Vgs of top & green is Vgs of bottom. Sometimes it is going to CCM mode to DCM mode. Also is there any way to make the stable voltage with the existing board for multiple loads?

    Below image red is inductor current , blue Vgs of bottom switch & green is Vds of bottom

    Whenever the Inductor current is approaching zero the mode is changing from CCM to DCM. The inductor waveform is also not the expected one. What might be the reason for this issue?

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    You can tie SYNCIN to VCC to have FPWM (forced PWM mode). SYNCIN has a 20kΩ internal pulldown, so the controller operates in diode emulation mode when the inductor current tries to go negative.

    Can you check what is causing the perturbations in the plots above (~40us period = 25kHz, which may correspond to the loop crossover frequency)? Also, check if this goes away when operating in FPWM.

    _

    Tim

  • 0 in reply to Timothy Hegarty
    TI__Guru 68757 points

    Looking at the waveforms again, there is large ringing on LO when the SW voltage transitions, which may be resulting in cross conduction. I think this is because the gate loop has high parasitic inductance, as the GND return path from the FET to the IC is sub-optimal. Can you change to a standard logic FET for the low side, as the L110 is a logic-level device with lower gate Miller plateau voltage of 3.3V. A standard logic FET will have a plateau of 4.5-5V and be more immune to ringing.

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    In LO the ringing is happening only when HO is turning on. Even with FPWM its the same.

    If you have the LTSpice model of LMQ1 , could you please share it?

    Till 1.35A (DCM mode) my inductor current is proper and once I enter the CCM mode the current is becoming as below like a sine way in positive Y axis only.( not going below zero)

    Regards,

    Kumar.

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar, 

    In diode emulation mode the low-side FET turns off to prevent negative current. How does it look at higher loads?

    It's the SW voltage rising that causes current to flow through Cdg of the low-side FET back to its gate – then the series parasitic inductance of the gate loop causes the ringing.

    Can you take load transient plots to see how Vout is looking? Also, send on the latest quickstart file.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    TI__Guru 68757 points

    We only have the PSPICE model - it's available in the product folder. We don't support LTspice. I can also send a simplified SIMPLIS model if that helps.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello Tim,

    In CCM mode sometime my FET is turning off when the inductor current reaches to zero and little negative.   Is the current flow through the Cgd will cause the Inductor current to behave like pulsated as shown in the below images? 

    4643.LM5146-Q1 Quickstart Tool r2 - 48Vin 12Vout 10A 400kHz.xlsm

    Please share the SIMPLIS file.

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar, it looks like an instability at light load or a noisy SW voltage waveform causing the zero-cross to trip in diode emulation mode. 

    What I mentioned earlier about the low-side gate drive applies in general. This likely isn't a contributing factor, as it behaves fine in your first plot (although this is at no load where the SW voltage dv/dt is benign, thus the current spike into the low-side gate is lower).

    -Tim

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    For the quickstart, are you using the correct Cout value (with ceramic derated for voltage) and have you entered the compensation component values from your schematic? This is critical to getting a valid bode plot. Also, I assume the LC post filter is not installed, as this will really complicate the voltage-mode control loop.

  • 0 in reply to Timothy Hegarty
    Prodigy 10 points

    Hello TIm,

    Yes I have removed the inductor which kept post LC filter. Yes the capacitance I'm using is same in the board( modified from schematic). The Compensation components in the schematic are modified and I'm using the  values based on the quick start calculator  in the board.

    Regards,

    Kumar

  • 0 in reply to Kranthi Reddy
    TI__Guru 68757 points

    Hi Kumar,

    Just make sure the Cout is accurately characterized, as this has a large effect on the control-to-output transfer function (and thus the required compensation network.

    Please confirm everything works fine in FPWM. If so, it must be some issue related to zero-cross detection. I recommend trying your circuit by modifying the LM5146 EVM (this will rule out a layout issue as well). This EVM is setup for 12V/8A/400kHz, close to your spec.

    Regards,

    Tim