TPS7H5005-SEP: PSPICE Simulation Issue

Hi Kamden,

The first thing I'd like you to try is replacing the TPS7H5005-SEP model with the TPS7H5001-SP model. The parts are functionally/electrically equivalent, but the TPS7H5001-SP model has a bug fix that may resolve convergence issues like this one.

Can you try this and let me know if the convergence issues successfully go away when you re-run your sim?

Thanks,

Sarah

I actually am already using the TPS7H5001-SP model due to this bug.

I see, in that case please give me some time to review your configuration and component selections and get back to you with feedback.

Hi Kamden,

Thanks for your patience with this one. I'm able to see some improvement by placing a diode across the S1 switch (SRA). Swapping your coupled inductors with a transformer part copied from the TPS7H5001-SP model's Push Pull schematic and updated with your values also seems to produce a better VOUT startup. I do still have to use the Autoconverge & resume 2 times during the initial phase of VOUT ramping, but it looks like VOUT rises well until OUTA hits the duty cycle limit about halfway through the startup.

Let me know if this feedback is enough to keep you moving, otherwise if technical feedback is needed on design choices the engineer who specializes on this part can give further guidance tomorrow.

Thanks,

Sarah

I appreciate you looking into it and making some improvements.  Do you think you can get me in touch with the engineer that specializes on this part?  I think there are some issues on how I am configuring the controller at this point.  Thanks!

Hey Kamden,

Im running your schematic with our SIMPLIS model at the moment, simply because its faster for me to debug your specific issue.
The schematic provided definitely has stability issues and that is likely what is causing the convergence issues in PSPICE.

To talk through the general philosophy on the controller's stability its set-up:
The controller uses current mode control through its CS_ILIM pin, and VSENSE pin.
It has an OTA for the error amplifier.
The RSC pin determines a slope compensation for the device. (implemented as a ramp subtracted from the output of the OTA).
The compensation scheme you are using adds a pole and a zero based on the resistors and capacitors used.

With all that being said, I can't say I'm super familiar with the converter you are trying to run.
I recognize the ACForward front end.
Note that this controller has an issue with ACF which is that the synchronous rectifier isn't on during start-up.
This means you want a bleeder resistor in parallel with the capacitor anyway.
The secondary side two bucks in parallel with one of the phases being coupled through the cap.
You also have a coupled inductor for the output inductors to try and reduce the current ripple
I dont know how this frequency response should normally look, but I will say I'm having trouble making it a stable system.

Was there a reason you choose this over a full-bridge with a current doubler?
That sort of converter would be more in line with what I would expect given the input/output requirements.

Thanks,
Daniel

Hi Dan, 

I appreciate the feedback!

I was trying to replicate something similar to this design that I saw in IEEE https://ieeexplore.ieee.org/document/10131436?arnumber=10131436 

I see that it is a stability error based on what you are saying so I will definitely look back at my average model simulation and see if I made some sort of error there because I was predicting a phase margin of around 89 deg based on my current set up. 

I also am now seeing how the active clamp will cause issues due to the synchronous rectification not operating until the SS cap reaches 1V so I will incorporate that bleeder resistor and an external diode for transformer reset during startup. 

In terms of why I didn't choose the full-bridge current doubler, I am honestly newer to the power electronics design space and wasn't entirely familiar with that topology.  This is definitely something I will look into and possibly modify my design to this topology. I'm going to continue to attempt to debug with current topology, but I appreciate all the info. It was very helpful!

-Kamden

Hey Kamden,

We do actually have a reference circuit for a full-bridge without the current-doubler:
https://www.ti.com/tool/PMP23200
All else fails you can start with that as a reference.

Keep us updated on if fixing the stability ends up fixing the problem.

Thanks,
Daniel