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LM43600 phase of switch relative to sync input

Other Parts Discussed in Thread: LM43600, LM5015

I'm working on a design where the LM43600 step-down is on the secondary side of a flyback.

To reduce ripple currents and noise in general (the board includes some precision ADCs etc.), it would be nice if the step-down draws current at the same time as the flyback rectifier diode conducts.  But I don't see any spec of the relative phase between sync input and power switch.

I think there may be a PLL inside, as it is capable to sync to higher or lower frequency than free-running one.

But it depends on the internal phase detector (in a 4046 PLL you have 3 different ones, for example).

The primary of the flyback is LM5015 (powered from 802.3af PoE), I can sync it from the LM43600 as well, but it has the unpredictable internal divide-by-2.  So it's easier to sync the flyback with 500 kHz pulses by small transformer (cost or size is not an issue in this project, it's not a mass-produced $9.99 consumer product but some special equipment in 19-inch rack size) from secondary to pirmary, and then sync the LM43600 with 250 kHz pulses from the flyback seconday winding.  But I don't know the phase relationship.  Ideally, the LM43600 step-down turn-on should be close in time to LM5015 flyback turn-off (secondary diode turn-on).  It doesn't have to be exact, but it shouldn't be 180deg out of phase as that would maximize ripple.

Any suggestions?

  • Hi Marek,

    Are you concerned about if there is a delay between the input at the sync pin and when the LM43600 switch turns on?

    Can you use an external clock, or a set of external clocks? Both the LM5015 and LM43600 will accept external synchronization signals (LM5015 datasheet says the RT pin can accept synchronization pulses).

  • Yes, I'd like to know how the LM43600 handles the sync input internally. Which edge (rising or falling) is important, and what is the delay from that edge to switch turn-on, assuming 250 kHz operation. The LM43600 switch should turn on close in time to when the LM5015 switch turns off. I can control both clocks separately, they come from a CPLD on the secondary side and one of them goes through a small pulse transformer to the LM5015 RT pin on primary side. There are two issues:
    - LM5015 has internal divide-by-2 (50% duty cycle limit) which I can't reset to known state using sync pulses
    - LM43600 has unknown delay from edge on sync input to switch turn-on
    I suspect in the LM43600 it is more complex than "sync edge terminates current oscillator cycle" as that would only sync to a higher frequency, that's why I suspect a PLL inside and need some specifics how it works.
    I could design around it by adding my own PLL to compare the two switchers phase and speed up or slow down the LM43600 (not sync, just vary RT current a little) to match the LM5015, but that seems overly complex.

    Thanks,
    Marek
  • Marek,
    The LM43600 syncs to the rising edge of the clock pulse i.e. in phase with the clock. There is a tiny bit of delay from clock rising edge to the SW turn on and that is attributed to filters and gate delays. There is a small additional delay from the mismatches in the charge pump that would be proportional to the frequency. All said and done, there is no frequency error on the LM43600. I understand this will be an issue because the ripple will add up.

    You could potentially add a phase delay to your external clock and feed it to the LM43600. Alternatively, you could try syncing the LM43600 from the secondary side using this approach: www.ti.com/.../snva004b.pdf. This would help you get the right phase for the clock to the LM43600.

    Regards,
    Akshay
  • OK, so it seems I can take the pulses from the flyback secondary, via a voltage divider for correct logic levels, to the LM43600 SYNC pin, and it should work as expected: rising edge (primary switch turn-off, secondary rectifier turn-on) triggers LM43600 switch turn-on. Small delays should be no problem, as long as flyback rectifier and LM43600 switch conduct roughly in-phase.

    Just one more question - the datasheet recommends the internal frequency set by RT to be the same as external clock. In reality, it will not be exactly the same due to tolerances, so what is the acceptable external clock frequency range (+/- percent relative to the the internal frequency) for correct synchronization? I don't see it specified in the datasheet.

    Thanks,
    Marek
  • I believe +/-10% should do it.

    Regards,
    Akshay