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TINA/Spice/SN65LVDS2: SN65LVDS2DBV spice model or alternative model.

Andrew Barriscale
Prodigy 20 points
Part Number: SN65LVDS2
Other Parts Discussed in Thread: TINA-TI

Tool/software: TINA-TI or Spice Models

I'm having trouble finding a spice model for SN65LVDS2DBV. The part has an IBIS model, however the IBIS model doesn't identify the pins of the part. It only identifies the input/output. I have talked to TI and they've said it isn't possible to  It there a solution to an alternative part or a way of getting the right model?

Thanks  

  • 0
    TI__Mastermind 38065 points
    Andrew,
    For digital devices like this one. the customary model is an IBIS model, which is a behavioral model of a device's digital inputs and outputs.
    The models are used in dedicated tools like Hyperlynx, where the goal is signal integrity simulations.

    Spice models are usually reserved for analog chips. Spice models of digital devices tend to not run efficiently in Spice simulators, and it is also difficult to extract meaningful results from a Spice sim of a digital device where the output can be a long bit stream.
    Therefor it is rare that we provide a Spice model for digital device like this one.

    That being said, we can sometimes provide a Spice model for a digital device like this one.
    To get this going, please contact your local TI sales representative and request a Spice model.
    Regards,
    John
  • 0
    TI__Mastermind 20460 points

    Hi Andrew,

    I don't understand your point about the IBIS model not identifying the pins of the part.

    The model has 2 components: DBV and D that correspond to the SOT23 and SOIC package options respectively.

    Each component has a [Pin] section that identifies each pin number, name and model associated to that pin.

    e.g.

    Component]     SN65LVDS2DBV
    [Manufacturer]  Texas Instruments Incorporated
    [Package]       |SOT23-5 package
    |               typ             min              max
    R_pkg           0.070           0.068            0.072     
    L_pkg           1.835nH         1.794nH          1.877nH
    C_pkg           0.282pF         0.276pF          0.287pF
    |
    |****************************************************************************
    |
    [Pin]   signal_name     model_name      R_pin   L_pin    C_pin     
    |
    1       VCC            POWER            0.06984  1.82932nH  0.29132pF
    2       GND            GND              0.00531  0.85671nH  0.22674pF
    3       A              RECEIVER_IN      0.06756  1.79361nH  0.28738pF
    4       B              RECEIVER_IN      0.06758  1.80143nH  0.27573pF
    5       R              RECEIVER_OUT     0.07225  1.87703nH  0.28366pF
    |  
    [Diff_pin]   inv_pin    vdiff      tdelay_typ    tdelay_min    tdelay_max    
    |
    | The 'A' pin is Diff_pin and the 'B' pin is the inv_pin
    |
    3            4          0.100      0             NA            NA
    |


    Please forgive the formattingasdfasdfasd

    Please forgive the formatting.

    Pins 3 and 4 are for the LVDS input, and pin 5 is the single ended output.

    Does this help?

    David Larkin

    Webench Design Center

  • 0 in reply to David Larkin
    Prodigy 20 points

    Hi David,

    I am using the model on PSpice. When associating the model to a schematic part, it requires the pins to be identified on the schematic part. A list of the schematics' pins is used to match the pins in the model. At the moment there are 5 pins needing to be identified (including power pins). Only one model can be used for a schematic part meaning all pins need to be in the same model. The input model is allowing me to identify "input" only. The output model allows me to identify "input", "output" and "enable". 

    In the IBIS model, there is no reference to pins A, B or R.  

    Thanks

    Andrew Barriscale

  • 0 in reply to Andrew Barriscale
    TI__Mastermind 20460 points

    Hi Andrew,

    Our prior experience informed us that PSPICE doesn't support IBIS, and that the translator somewhat supports just input buffers.

    Doing a quick search, I see that version 16.6 claims to support IBIS, including VT waveforms. I don't have enough familiarity with PSPICE to offer any help.

    The IBIS LVDS2 model is proper, so that would suggest that there must be some hooks or options in the 16.6 version to map the pins properly.

    David