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TIDA-00915: the clock signal connecte a capacitor to the Sigma-Delta ADC converter

Part Number: TIDA-00915
Other Parts Discussed in Thread: CDCLVC1102,

Hello, TI Engineer:

Recently read the "Three-Phase High PWM Frequency GaN Inverter Design TIDA-00915 Reference" reference design. There are some details about the high speed circuit inside. Do not understand, please point out.

The circuit diagram is shown below. Tms320f28377d's "PWM output" serves as the clock signal(20.0MHz), providing the clock signal via buffer (CDCLVC1102PW) for 4 Sigma-Delta ADC converters (only 2 painted in the picture). The designers consider impedance matching, parallel two 100 ohm and series 22 ohm resistors to realize impedance matching. But why would a 0.1uF capacitor be connected in series between the CLK line and the DATA line?

 I have four questions:

1.Is the impedance matching required to connect the 0.1uF capacitor to the CLK line and the data line? How is capacitive capacitance calculated? Can you recommend a document?Not all of the The signal lines are connected to the 0.1uF capacitor, You can see,the DC bus voltage measurement of the CLK is not connect ed. Is it missing or something else? 

2.Designers are connected in series with 0 ohm resistance, which is needed for debugging. (28377 Sigma-Delta ADC mode 2 can not use clock signal), or are there other reasons? How many 0 ohm resistances are connected in series so that they don't worry about impedance matching?

3.About when do you need to consider impedance matching? Some documents say that for 20MHz signals, PCB traces more than 50mm to consider. Another document says that the rising edge and the falling edge of the signal are less than 6 times the signal delay needed to be considered. Do you have any suggestions for when to consider? Because the TI reference circuit "uses the SAR and sigma delta ADC as a reference design for integrated diagnostic functions in protective relays, TIDA-00810" does not consider impedance matching in the same circuit.

4.How to evaluate CDCLVC1102PW's drive capability, CDCLVC1102PW's CLK pin drives 4 slices of AMC1306, and also provides clock signals for at least four Sigma-Delta ADC converters on tms320f28377d chips.How many Sigma-Delta ADC converter chips andthe sigma delta filter module can CDCLVC1102PW be drived?

I'm looking forward to hearing from you soon

At this site, you can download the Design Files

  • Hello Tina,

    looks like this a modified schematic from the Altium design files. Please see the variants information in Altium, which show that some resistors are DNP.

    (1) I had the 0.1uF capacitor on the data signal, it does not have an effect in the impedance matching of the data signal. The 0.1uF capacitor would be low impedance to the 20Mhz data signal. This was kept for testing. Please remove this capacitor and replace with a short. Thanks, I will add a note in design guide to make it clear. 

    (2) Some resistors are for debugging.

    R12 and R16 on clock lines are DNP when using the Manchester encoded version of AMC1306 as there is no need to give the clock back to C2000 when data is Manchester encoded.

    R4, R7, R15 and R17 are used for debugging either open or short according to the need. This can be eliminated.

    R5, R13, R3,R6 are for impedance matching (series termination). 

    Also,  R1 and  R8, or  R11 and R14 are placed for parallel termination, this should not be placed when using series termination. After testing i have seen that series termination works best.

    (3) I had long distance and also a cable between AMC1306 and C2000 about 10cm. The issues due to propagation delay is eliminated by using Manchester encoded data. However impedance matching is required for signal integrity. Example: one of the problems I have seen with out impedance matching is excessive ringing at the signal edges. I have done only a rough impedance matching using the resistors, but I have not done the impedance control in the PCB manufacturing. At 20Mhz one may not see a problem depending on the board and cable, I would still put it as provision.

    also note, CDCLVC1102 has a internal series termination resistance for 50Ohm. You may need to add to this.

    (4) TIDA-00915-C does have provision for 4 clock input to the C2000, but since I am using the Manchester version of the AMC1306, I have DNP resistors on these clock lines. effectively I have only 4 AMC1306, being driven. This works very well for TIDA-00915, unfortunately, I do not have any info on the max number of AMC1306. Please do post on the Clock and Timing Forum about max number of loads for CDCLVC1102.



  • I got it,except "CDCLVC1102 has a internal series termination resistance for 50Ohm. You may need to add to this".Could you explain that again?

    Thank you very much for your reply.

  • Hello,

    In the datasheet of CDCLVC1102 it has an output impedance of 45Ohms when powered from 3.3V, the PCB board trace is made for 67 Ohms. then the series resistance that has to added at the out put of CDCLVC1102 is 67-45 = 22Ohms.

    If there is no series resistance externally for CDCLVC1102, does not mean there is no impedance matching on the board, as there is some series impedance internally.