TINA/Spice/CSD86330Q3D: Significant GS Capacity deviation

Helli Nikhil,

See Datasheet Chapter:

5.5 Electrical Characteristics

DYNAMIC CHARACTERISTICS

CISS Input Capacitance 1280pF Typ (this is what i meant with Gate-Source Capacity)

I believed that the specified value for CISS is valid for both: the Control FET and the Sync FET

But what i found in the shown Simulation is that the CISS of Syc FEF is more than twice as Big as the CISS of the Control FET

This is insufficient. Either for the related TINA Model OR for the Data Sheet

BR Norbert

Norbert, 

I work with the FET group. I'm looking into this for you and hope to have an answer shortly. 

Norbert,
I confirmed that for the PSPICE model, the CISS accurately reflects the datasheet values of ~710 (HS) and ~1280 (LS). This is also the case in the datasheet.

The sync and control FET should not be the same value.

Does this agree with what you are seeing in the TINA model?

Brett,

now since the online datasheet all of a sudden provides separate values for Q1 and Q2  I can agree to that what I am seeing in the Simulation and the Datasheet.

Thanks for having a look into this.

BR

Norbert