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WEBENCH® Tools/LMZ10503: Webench design re-comp and sim difference

Part Number: LMZ10503

Tool/software: WEBENCH® Design Tools

Hello,

I'm using Webench designer to simulate a simple circuit using LMZ10503 part.

If I simulate my circuit with the SIM tab and show the bode plot, my design seems to be unstable (10° phase margin).

But if I go to the re-comp tab, my design seems more stable (38° phase margin) with the same value of components.

The two results are not the same with the same design, could someone explain this difference and what is the real phase margin of my design.

Thanks

Matthieu Baque

  • Hi Matthieu Baque,

    Thank you for reporting this issue.

    The simulation uses "Averaged SPICE model" for generating the bode plot. While the re-compensation, Op-Val table and Charts section in WEBENCH use "Equation based model". Ideally these both models should match very closely with each other and to the actual device bench data. But in this particular case there seems to be significant difference between the two. We will look into the issue and try to resolve it.

    In the mean time, I would recommend you to use the compensation component values as recommended by the Table 4 (page 18 and 19) in the datasheet. Larger output capacitance with higher ESR will give you better phase margin and smaller output capacitance will have higher bandwidth. You can have a good balanced design by choosing Cout= 100uF ESR = 5m with 5V rating, Rcomp=1k, Ccomp=220p. Rfbt=49.9k, Rfbb=205k. You may use the below design:
    webench.ti.com/.../SDP.cgi

    Regards,
    Srikanth Pam | Online Design Tools
  • Hi Matthieu Baque,

    We are looking into the Bode plot issue. We will get back to you soon.

    Regards,

    Anurag

  • Hi,
    Do you have some news about this issue?

    I need this information to calculate the compensation. I tried to use the application report SNVA417E but I don't know how to calculate Fesr in equation 6.

    In all cases, I want to simulate my design to adjust compensation but I don't know if the Pspice model is correct.

    Thanks
    Regards
    Matthieu Baque
  • HI Matthieu Baque,

    The pspice model needs to be revised as the simulation results are not matching with Opvals values (Crossover and phase margin).

    I am looking into it. Will keep you posted once the issue is resolved.

    Regards,

    Anurag

  • Matthieu,
    Please send me your exact requirements and we can take a look at recommending component values for you.
    Thanks,
    Akshay
  • Hi Matthieu Baque,

    Please use the re-comp designer for designing components for your application.

    Regards,

    Anurag

  • Hi Akshay,

    My design is Vin = 3.3V, Vout = 1V. Iout max 3A. All capacitors are ceramic.

    Cout is one 100 µF with ESR between 1mOhms and 40 mOhms + one 4.7 µF with ESR between 1mOhms and 20 mOhms.

    These capacitors are the capacitors close to the LMZ10503 but if I add all decoupling capacitors of my circuits, I have in more :

    - Another 100 µF with ESR between 1mOhms and 40 mOhms

    - One 47 µF with ESR between 1mOhms and 40 mOhms

    - Two more 4.7 µF with ESR between 1mOhms and 20 mOhms

    - Three 470 nF with ESR between 1mOhms and 20 mOhms

    I need to calculate Rfbt, Ccomp and Rcomp.

    If you have a method to calculate it because I tried with SNVA417E but not possible because I don't have only one type of capacitor. More of that, I don't know what is Fesr in the application report.

    Many thanks

    Matthieu Baque

  • Hi Anurag,
    I tried but I can't use the tool because my design have different type of output capacitors.

    So, I'm stuck
    Matthieu Baque
  • Hi Matthieu,
    You can try increasing the capacitance by lumping these capacitances together and enter the lumped capacitor and ESR value into the section called Power Stage Components(It should be on the left side inside the tool) inside the Recompensation designer . You can then autocalculate the value of Rcomp, Ccomp based on your Cross over and phase margin requirements. Once you are ok with those results, you can then take them to the Spice model and enter a more realistic parallel capacitor based model (for various types of parallel caps) and simulate to verify if you are achieving the desired results.
    Regards,
    Gerold
  • Hi Gerold,

    Yes but the first issue is that the results between compensation design and Spice simulation are different.

    With compensation design Iout = 0.5A Cout = 262.5uF with total ESR 1.33mOhms. I found 50.8° phase margin with compensation designer.

    But if I use same value in Pspice and put calculated value of compensation components, I found a phase margin of 24°.

    Regards

    Matthieu Baque

  • Hi,

    Ok to use the re-comp resigner but I'm still have a problem because my spice simulation is wrong and I can't trust it. How can I correct the spice simuation?

    Matthieu Baque