Other Parts Discussed in Thread: LMX2594, LMK04828
In the document Multichannel JESD204B 15-GHz Clocking Reference Design (Rev. A) says:
" Because the LMX2594 devices are being used in master mode, SysRefReq signal needs to be at logic high. To ensure this, the respective SDCLKout pins are made conditionally low. Prior to feeding this signal to a balun, the positive and negative signals of the differential pair are exchanged. This exchange gives a continuous high logic at the balun output and serves as the SysRefReq signal "
Can you confirm this since I could not find information on the LMX2594 datasheet. Or maybe it is implied by JESD204B standard?
Looking at the schematic, I follow pin3 of U1=LMK04828. It is SDCLKout1+. It is routed to pin4 of U23=DS90LV028AQMA. So this agrees whith the quotaion above.
Looking at the CAD documents on the other hand the schematic is OK, pin3 of U1 is connected to pin4 of U23. However in the PCB assuming R27 and R287 is inserted pin3 of U1 gets connected to pin3 of U23.
Which one should I take as reference? The PCB od Schematic? U1.3 -> U23.4 OR U1.3 -> U23.3?