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TIDA-00199: Effect of Switching Harmonics on other signals

Jamiryo
Intellectual 310 points
Part Number: TIDA-00199
Other Parts Discussed in Thread: LM5160

Hi everyone, I created a circuit which have 6 SiC mosfet, DC link capacitors and smps transformer( like TIDA-00199 design) for driving (ISO5852 IC Drivers used) leg SiC mosfets. Three of outputs are driving top mosfets, other one is driving bottom mosfets thanks to SMPS,

LM5160 is driving to würth 750315038 transformer and there are four isolated supply as +20V and -4V.

LM5160 specs:

Switching Frequency :275kHz,

Input voltage :24V;

Transformer Output Voltage : +20/-4V in each output (There are no harmonics in isolated supplies)

Question:

When I turned off the SMPS and when I checked the 3.3V primary gate driver signals, There are no harmonics or other parasitic effects on it. 

When I turned on the SMPS and when I checked the 3.3V primary gate driver signals, There are harmonics around 275kHz. These harmonics are also effecting to secondary gate driving signals(+20V,-4V) in each driver. Thus, It is effecting to Mosfets.

I thought to seperate grounds for 3.3V signals and 24V, It can work but I don't want to do that.

Consequently, SMPS switching harmonics effecting to all non-isolated sections on pcb.

Do you have ideas to fix it ?

  • 0
    TI__Expert 4100 points
    Hello,
    I will forward your question to the responsible engineer.
    Regards
    Brani
  • 0
    TI__Guru 69997 points
    Hi Kaan,

    My understanding is that there is coupling from the Fly-Buck converter to the 3.3V primary-referenced gate drive signals. Can you share the schematic and PCB layout?

    What is providing the 3.3V primary-referenced gate drive signals and are the signals routed close to the Fly-Buck converter?

    Regards,
    Tim
  • 0 in reply to Timothy Hegarty
    Intellectual 310 points

    Hi Tim,


    Sorry for late, 24V for Flybuck converter and 3.3V primary referenced signals sharing the same grounds. 3.3V PWM gate drive signals directly coming from the header and it is going to ISO5852 driver IC. 

    I added schematic and pcb layouts. No they are not close to fly-buck.

  • 0 in reply to Timothy Hegarty
    Intellectual 310 points
    Do you have an idea ?
  • 0 in reply to Jamiryo
    TI__Guru 69997 points
    Hi Kaan,

    I notice some of the output buses are crossing the signal lines. Note that the high-side outputs have a dv/dt related to switching of the SiC MOSFETs. Is this a 2-layer PCB? A multi-layer board would allow the signal traces to be shielded from the high dv/dt traces.

    Note that the trace from the input capcaitor to the VIN pin of the IC is very narrow - this should be made thicker to minimize parasitic inductance of the input capacitor loop.

    Regards,
    Tim
  • 0 in reply to Timothy Hegarty
    Intellectual 310 points
    Hi Timoty,
    Thank you for your answer, I will make the VIN trace thicker and I will seperate the 24V supply GND of IC from Non-isolated section.Tomorrow, I will let you you know the results. Do you have other suggestions ?
  • 0 in reply to Jamiryo
    TI__Guru 69997 points
    Hi Kaan,

    I recommned using a GND plane between the secondary-side output traces and the 3.3V gate drive signal traces. At the very least, the traces should intersect only at right angles.

    Regards,
    Tim
  • 0 in reply to Timothy Hegarty
    Intellectual 310 points

    Hi again,

    I attached graphs about on and off cycle of sic mosfet, I switched it at 10khz.

    Green: V-ds,

    Blue   :Current passing through the mosfet,

    Purple:Vgs,

    Yellow:Primary firing signal,

    As you see in graph, there are parasitics on primary and secondary firing signals because of smps, but when I checked the Vds and Id, there are less harmonics,

    what do you think about effect of these parasitics on efficiency and operations ??? 

    Turnon;

    TURN-OFF;

    SMPS parasits when mosfet on( Half cycle of smps);

    SMPS parasits when mosfet off( Half cycle of smps);

  • 0 in reply to Jamiryo
    TI__Guru 69997 points

    Hi Kaan,

    Looks acceptable. In addition to reducing the coupling from power to control sections, you can also reduce the parasitics of the power stage to alleviate ringing - position a ceramic decouplling capacitor as close as possible to the SiC FETs and place an image GND plane immediately below the power stage.

    Regards,

    Tim

  • 0 in reply to Timothy Hegarty
    Intellectual 310 points
    Thank you Tim, can I we talk from PM ? I need to ask something
  • 0 in reply to Timothy Hegarty
    Intellectual 310 points

    I put DC link capacitors. Thus, I increased DC link voltage around 310V and I added 37R load to one mosfet. Then, I applied 100us single pulse but there are much ringing on Vds voltage. Also It affected the Vgs voltage. When I checked the peaks of ringings. I measured around 3.65us (273khz-SMPS frequency). 

    I dont know maybe I thought wrong.

    I added scope image.

    Should I use RC snubber ?

    Green : Vds,

    Blue: Id,

    Purple: Vgs,

    Yellow:Primary pwm,

    Green : Vds,

    Blue: Id,

    Purple: Vgs,

    Yellow:SMPS switching,

  • 0 in reply to Jamiryo
    TI__Guru 69997 points
    Hello Kaan,

    I doubt the switching frequency of the SMPS is affecting the ringing of the SW node. The SW node oscillation is effective a resonance between the parasitic inductance in the loop formed by the input cap and SiC MOSFETs and the parasitic output capacitance of the MOSFETs. The key is to place a ceramic cap very close to the SiC devices and place a GND plane underneath - this reduces the parastic inductance and thus the energy stored in the described parasitic LC circuit.

    Regards,
    Tim